Method of forming semiconductor structure

Abstract

The present disclosure relates to a method of forming a semiconductor structure. The method includes providing a structure having a gate stack; a first gate spacer; a second gate spacer on one of the first gate spacers and having an upper part on a lower part; dummy spacers; an etch stop layer; and a dummy cover. The method further includes removing the dummy cover to form a first cavity between the gate stack and the first gate spacer; removing the dummy spacers to form a second cavity on the lower part and between the etching stop layer and the upper part; depositing a layer of decomposable material into the first cavity and the second cavity; depositing a sealing layer on the etch stop layer, the first gate spacer, the second gate spacer, and the decomposable material layer; and removing the decomposable material layer to re-form at least part of the first cavity and the second cavity.

Description

technical field [0001] Embodiments of the present invention relate to a semiconductor manufacturing process and its structure. Embodiments of the present invention more particularly relate to increasing the isolation between the gate and source / drain contacts and between the gate and adjacent conductors (such as metal lines above the gate) and stray capacitance in field effect transistors. Descent method and structure. Background technique [0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have resulted in each generation of integrated circuits having smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (eg, the number of interconnect devices per unit chip area) generally increases as geometric dimensions (eg, the smallest component or circuit that can be produced by the fabrication process employed...

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