Implementation method and system for vsetli instruction in risv_v vector instruction set

An implementation method and instruction set technology, applied in the field of CPU, can solve the problems of increased execution cycle, power consumption, low CPU execution efficiency, etc., and achieve the effect of reducing power consumption, reducing execution cycle, and reducing latency

Pending Publication Date: 2021-10-01
GUANGDONG STARFIVE TECH LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to achieve simplicity, the easiest way is to refresh the pipeline when the vsetli instruction graduates. At the same time, regardless of the inactive element part of the execution unit, it is sent to the execution unit for execution, resulting in an increase in the execution cycle.
[0003] The existing vsetli instruction needs to refresh the pipeline when it graduates, resulting in low CPU execution efficiency. The Vector instruction also executes the inactive element part in the execution unit, and finally selects the data through the mask. In fact, the mask data is originally There is no need to enter the execution unit, which results in a waste of power consumption and an increase in the execution cycle of the instruction

Method used

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  • Implementation method and system for vsetli instruction in risv_v vector instruction set
  • Implementation method and system for vsetli instruction in risv_v vector instruction set
  • Implementation method and system for vsetli instruction in risv_v vector instruction set

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Embodiment 1

[0027] This embodiment discloses as figure 1 The implementation method of a risv_v vector instruction set vsetli instruction shown includes the following steps:

[0028] When the S1CPU executes out of order, allocate vectag[n:0] information in the rename module to determine whether the instruction is vsetli;

[0029] S2 If the instruction is vsetli, then vectag+1, if it is not a vsetli instruction, then the vectag remains unchanged;

[0030] S3 is sent to the execution unit, and the vsetli instruction is distributed to the csr module; corresponding to other vector instructions, it is distributed to the vpu module;

[0031] S4 judges that when the instruction vectag is consistent with the vectag broadcast by the ROB, the instruction is sent from the reserver station to the execution unit;

[0032] The execution of the S5 instruction is completed, and in the ROB module, graduations are performed sequentially, and the register vectag is updated at the time of graduation, and th...

Embodiment 2

[0039] This embodiment refers to the out-of-order CPU, and its basic structure is as follows figure 2 As shown, this embodiment discloses an implementation system of a risv_v vector instruction set vsetli instruction, which includes four modules: rename, dispatch, ROB and vpu.

[0040] The rename module of this embodiment will allocate a vectag[n:0] information in the rename module. If it is vsetli, then vectag+1, and the vectag of the non-vsetli instruction remains unchanged. The purpose of doing this is for the vpu unit The command to be executed can be sent to the execution unit for execution only when the vectag of the command in the reserve station is consistent with the vectage broadcast by the csr.

[0041] The function of the dispatch module in this embodiment is to distribute the instructions to different datapaths according to the types of the instructions, and to distribute to the csr module corresponding to the vsetli instruction; to distribute to the vpu module c...

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Abstract

The invention relates to the technical field of CPUs, in particular to an implementation method and system for a vsetli instruction in a risv_v vector instruction set. The method comprises the steps that: vectag [n: 0] information is distributed in a rename module during out-of-order execution of a CPU, and whether the instruction is vsetli or not is judged; if the instruction is a vsetli instruction, 1 is added to vectag, and if the instruction is a non-vsetli instruction, vectag remains unchanged; the vsetli instruction is transmitted to an execution unit, and the vsetli instruction is distributed to a csr module; corresponding other vector instructions are distributed to a vpu module; when it is judged that the vectag of the instruction is consistent with the vectag broadcasted by an ROB, the instruction is transmitted to the execution unit from a reserver station; and after the instruction execution is completed, graduating is carried out in sequence in the ROB module, the vectag of a register is updated during graduation, and the execution is ended. According to the method, the execution efficiency for a non-vsetl {i} Vector instruction is high. Data is selected in a mask mode, the power consumption is reduced, the execution period can be shortened, and latency is reduced. The method and the system have a very wide market application prospect.

Description

technical field [0001] The invention relates to the technical field of CPUs, in particular to a method and system for realizing vsetli instructions of a risv_v vector instruction set. Background technique [0002] The isc_v instruction set has only recently released a complete instruction set, and there are basically no implementation methods that can be referred to at present. In order to achieve simplicity, the easiest way is to refresh the pipeline when the vsetli instruction graduates, and at the same time, regardless of the inactive element part of the execution unit, it is sent to the execution unit for execution, resulting in an increase in the execution cycle. [0003] The existing vsetli instruction needs to refresh the pipeline when it graduates, resulting in low CPU execution efficiency. The Vector instruction also executes the inactive element part in the execution unit, and finally selects the data through the mask. In fact, the mask data is originally There is...

Claims

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Application Information

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IPC IPC(8): G06F9/30G06F9/38G06F9/50
CPCG06F9/30098G06F9/3867G06F9/5027Y02D10/00
Inventor 李长林
Owner GUANGDONG STARFIVE TECH LTD
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