Method for realizing inter-chip consistency by using adaptive granularity directory table

Abstract

The invention discloses a method for realizing inter-chip consistency by using a self-adaptive granularity directory table. The method comprises the following steps: adopting a self-adaptive granularity directory table, which comprises a coarse granularity directory table and a fine granularity directory table; recording a memory block used for any one of the local processor core and the remote processor core by using the coarse granularity directory table, wherein an address space range corresponding to the coarse granularity directory table is the memory block; and recording memory blocks for both a local processor core and a remote processor core by using the fine granularity directory table. The coarse granularity directory table is used for covering the whole local memory space, and then the fine granularity directory table is used for improving the filtering precision of a small number of local and remote shared addresses, so that relatively high performance can be achieved with relatively low capacity; and a forward fine granularity directory table and a reverse fine granularity directory table can be the same directory table, and only one item representing the direction of the directory table is added in the table items, so that hardware resources can be flexibly applied according to actual conditions.

Description

technical field [0001] The invention relates to the technical field of methods for realizing inter-slice consistency, in particular to a method for realizing inter-slice consistency by using an adaptive granularity directory table. Background technique [0002] In a NUMA system, cache consistency must be maintained between caches on all processor chips, that is, when a processor core reads data, it must be able to see that all processors on the NUMA system check the modification of this data, including saving The modification in the remote cache requires monitoring of the remote cache. [0003] Each processor chip in a NUMA system has a large memory address space. If each cache line occupies a bit in the directory table, it indicates whether it is possible to have a copy in the remote cache. Taking the cache line width of 512 bits as an example, if The local memory capacity is 32GB, which contains a total of 512M cache lines. Each cache line occupies 1 bit in the directory ...

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Problems solved by technology

[0003] Each processor chip in a NUMA system has a large memory address space. If each cache line occupies a bit in the directory table, it indicates whether it is possible to have a copy in the remote cache. Taking the cache line width of 512 bits as an example, if The local memory capacity is 32GB, which contains a total of 512M cache lines. Each cache line occupies 1 bit in the directory table. We call it a fine-grained directory table. The total capacity of the directory table is as high as 64MB, which is difficult to fit into the on-chip RAM. In, and if placed outside the chip, it will increase the access delay

If a bit in the directory table is used to indicate a larger address access, for example, 1 bit indicates whether the data of a 4KB page is likely to be stored in the remote cache, we call it a coarse-grained directory table, and the capacity of the directory table can be reduced to 1MB , but the filtering effect of the directory table on unnecessary monitoring will be reduced, because any cache line in a page is stored in the remote cache, and access to other cache lines in the page must also be monitored remotely, although this monitoring Doomed not to hit; In addition, the maintenance of the coarse-grained directory table is also troublesome, because there may be multiple cache lines in the same page being obtained by the remote cache, but the coarse-grained directory table does not record in detail which rows are allocated, so when there are cache lines from When the remote cache is released, it cannot be determined whether there are cache lines that have not been released in the remote cache on this page, and it is impossible to directly determine whether the corresponding directory entry can be released. It is necessary to actively issue a monitoring command to the remote chip to confirm whether it is still available. There are cache lines that have not been released, and the traditional directory table uses a fixed granularity: if it is not fine-grained to obtain high precision, it will increase the capacity of the directory table; if it is not coarse-grained, the capacity of the directory table will be reduced but the filtering effect on invalid monitoring will be lost

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