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Capacitor with high-dielectric-constant dielectric and thick electrode and fabrication method thereof

A manufacturing method and capacitor technology, applied in the field of capacitors, can solve problems such as the leakage current of electrodes 1104, and achieve the effect of preventing the increase of contact resistance

Inactive Publication Date: 2004-01-21
NEC ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0030] The leakage current near the top corner of the lower electrode 1104 and on its side is also not considered.

Method used

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  • Capacitor with high-dielectric-constant dielectric and thick electrode and fabrication method thereof
  • Capacitor with high-dielectric-constant dielectric and thick electrode and fabrication method thereof
  • Capacitor with high-dielectric-constant dielectric and thick electrode and fabrication method thereof

Examples

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Effect test

no. 1 example

[0111] image 3 The structure of a capacitor for a GB class DRAM according to the first embodiment of the present invention is shown.

[0112] image 3 In the present invention, an interlayer insulating layer 102 with a thickness of 500 nm is formed on the main surface of an n-type single crystal silicon (Si) substrate 101 having a resistivity of 0.01 Ωcm. SiO 2 It has a contact hole 115 filled with a contact plug 103 made of phosphorus-doped polysilicon. The bottom surface of the contact plug 103 is in contact with and electrically connected to the substrate 101 , and the top of the contact plug 103 is exposed from the interlayer insulating layer 102 .

[0113] although image 3 Not shown in the middle, a diffusion region is generally formed in the substrate 101, and a contact plug 103 is in contact with and electrically connected to the diffusion region.

[0114] A bottom electrode 104 with a thickness of 400 nm is formed on the interlayer insulating layer 102 and is in co...

no. 2 example

[0146] Figure 7 The configuration of a capacitor for a GB class DRAM according to a second embodiment of the present invention is shown.

[0147] The capacitor according to the second embodiment of the present invention has the same structure as the first embodiment except that the thickness of the portion 102a of the interlayer insulating layer 102 is thicker than that of the rest of the layer 102. A portion 102 a of the interlayer insulating layer 102 surrounds the contact plug 103 and is located just below the lower electrode 104 . A portion 102a of the interlayer insulating layer 102 is 500 nm thick and the rest of the interlayer insulating layer 102 is 300 nm thick.

[0148] The capacitor according to the second embodiment was manufactured in the following manner.

[0149] First, use the Figures 4A to 4D Made by the same process steps Figure 8A structure shown.

[0150] After that, if Figure 8B As shown, using the insulating cap layer 105 as a mask, the interlay...

no. 3 example

[0159] Figure 11A The structure of a capacitor for a GB class DRAM according to a third embodiment of the present invention is shown.

[0160] The structure of the capacitor according to the third embodiment is the same as that of the capacitor according to the first embodiment, except that a diffusion barrier layer 110a is additionally formed between the polysilicon contact plug 103 and the lower electrode 104 . The diffusion barrier layer 110 a is located in the contact hole 115 of the interlayer insulating layer 102 .

[0161] Obviously, there are the same advantages as the first embodiment.

[0162] Also, the diffusion barrier layer 110 a prevents silicon atoms contained in the polysilicon contact plug 103 from diffusing into the lower electrode 104 . As a result, an additional advantage is that defects due to silicon diffusion can be prevented.

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Abstract

A capacitor with a high dielectric-constant dielectric and a thick lower electrode decreases the leakage current. The thick lower electrode is on an interlayer insulating layer. Typically, the interlayer insulating layer is formed on or over a semiconductor substrate. The lower electrode has a top face, a bottom face, and side faces. The bottom face of the lower electrode is adjacent to the interlayer insulating layer. An insulating cap or cover layer is on and contacts the top face of the lower electrode. The insulating cap or cover layer covers the top face of the lower electrode and uncovers the side faces of the lower electrode. A capacitor dielectric layer covers and contacts the side faces of the lower electrode and the insulating cap or cover layer. An upper electrode is on and contacts the capacitor dielectric layer. The capacitor dielectric layer is sandwiched by the upper and lower electrodes to thereby constitute a capacitor structure.

Description

technical field [0001] The present invention relates to capacitors formed on semiconductor substrates, and more particularly to capacitors having a high dielectric constant capacitor dielectric and a thick capacitor electrode or electrodes, preferably for GB (gigabit) level dynamic random access In the memory (DRAM). Background technique [0002] In recent years, the integration degree of semiconductor integrated circuits (ICs) such as DRAMs has become higher and higher, and therefore, electronic components in the ICs have become more and more miniaturized. [0003] Each storage capacitor of DRAM is required to have a capacitance of 30fF in order to realize its information storage function, and even when the integration scale of IC becomes very high, the size of the storage capacitor becomes extremely small. [0004] To meet this requirement, in general, increasing the thickness of the lower electrode to utilize the sides of the lower electrode, or reducing the thickness of...

Claims

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Application Information

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IPC IPC(8): H01L27/04H01L21/02H01L21/822H01L21/8242H01L27/108
CPCH01L27/10852H01L28/75H01L28/55H10B12/033
Inventor 山口弘
Owner NEC ELECTRONICS CORP