Method for reducing contact resistance in high depth ratio self alignment etching

Abstract

The invention relates to a method for reducing the contact resistance in self-aligned contact etching with high ratio of depth to width. The method includes the processes as following: a) by using the first etching gas which contains fluorocarbon with low F / C ratio, self-aligned etching is performed on the structure of semiconductor devices, and contact holes are formed; b) the contact holes formed are etched and cleaned; and c) by using the second etching gas which contains fluorocarbon with high F / C ratio, the contact holes are slightly etched again, and the remained polymer films on the bottom of the contact holes are removed. The method has the advantages of preventing the increase of the contact resistance of the contact holes, thereby improving the performance stability of semiconductor devices and enlarging the processing window and the processing capacity of self-aligned contact techniques.

Description

technical field [0001] [1] The present invention relates to a method for forming a contact of a semiconductor device, in particular, to a method for reducing contact resistance in high aspect ratio Self-Aligned Contact (SAC) etching in which conventional self-aligned After the alignment etch step, a self-aligned slight etch step is added to remove the deposited polymer layer at the bottom of the contact hole, thereby reducing the contact resistance of the contact hole, thereby increasing the processing window and processing of the self-aligned contact process. capabilities, and improve the stability and reliability of semiconductor device performance. Background technique [0002] [2] With the continuous shrinking of the device size, the problem of dielectric etching caused by the shrinking feature size and high aspect ratio in self-aligned contact etching is becoming more and more serious, which often leads to the problem of reducing the etching process window. [0003] [3...

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Problems solved by technology

[0002] [2] With the continuous shrinking of device size, the dielectric etching problem caused by the shrinking feature size and high aspect ratio in self-aligned contact etching is becoming more and more serious, which often leads to the problem of reducing the etching process window

Because, once damaged, the gate conductive layer will be exposed, which may cause a short circuit in the subsequent process.

[0004] [4] However, if high fluorocarbon ratio fluorocarbons such as CF 4 、C 2 f 6 、C 3 f 8 etc. as etching gas for SAC etching, it is often difficult to meet the requirements of the above two aspects at the same time due to the high aspect ratio of the contact hole

[0007] [7] However, using the above-mentioned fluorocarbons with a low fluorocarbon ratio (such as C 5 f 8 ) has the disadvantage that it produces a highly cross-linked and insulating deposited polymer film on the sidewalls and bottom of the contact hole during the etch process, which partially remains on the contact even after a post-etch cleaning step. hole bottom

Therefore, resulting in a contact resistance R at the bottom of the contact hole c Significant rise, making the performance of semiconductor devices unstable and the processing window becomes smaller

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