FPGA (Field Programmable Gate Array) for improving reliability of key configuration code stream by multiplexing buffer memory

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) for improving the reliability of a key configuration code stream by multiplexing a buffer memory, and relates to the technical field of FPGAs. The FPGA stores a key configuration chain by using a configuration cache, and correctness of the content of the key configuration chain is ensured through an ECC (Error Correct Code) checking function of the configuration cache. Therefore, when the FPGA runs normally, the control circuit reads out and writes the key configuration chain in the configuration cache into the corresponding configuration block at preset time intervals to update the key configuration chain, so that the accuracy of the content of the key configuration chain is ensured, and the operation reliability of the FPGA is improved.

Description

technical field [0001] The invention relates to the field of FPGA technology, in particular to an FPGA which improves the reliability of key configuration streams by multiplexing buffer memory. Background technique [0002] With the development of VLSI technology, FPGA chips (Field Programmable Gate Array, Field Programmable Gate Array) have been widely used relying on their superior interface performance, rich logic and IP resources, and flexible and convenient field programmability. [0003] There are configurable modules and routing resources inside the FPGA chip. When the user design is mapped to the FPGA chip, the user design can determine the functions and routing resources implemented by the configurable modules inside the FPGA chip by defining the configuration content (configuration bit content) The routing path chosen defines the function implemented by the FPGA chip. The FPGA design software processes the user design input through synthesis, layout, and wiring, a...

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Problems solved by technology

[0004] Affected by external factors such as power supply, radiation, electromagnetic, and particles, FPGA chips are prone to SEU (Single Event Upset) problems, which will cause configuration content to be flipped incorrectly, and circuit functions to malfunction. Therefore, in high-reliability FPGA chips In the field of application, improving the reliability of configuration content is an important issue

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