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PFR flash memory expansion device and method

A technology of expansion device and flash memory, which is applied in the field of servers, can solve problems such as insufficient space and inability to support, and achieve the effects of simple structure, wide application prospects, and reliable design principles

Active Publication Date: 2021-11-05
SUZHOU LANGCHAO INTELLIGENT TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The NOR Flash packaged in SO16 on the market only supports a maximum capacity of 1Gb. If you want to provide additional customized functions and match the PFR architecture to exceed 1Gb, you will face the dilemma of insufficient space and cannot support it.

Method used

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  • PFR flash memory expansion device and method
  • PFR flash memory expansion device and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0048] In the existing PFR flash memory architecture, both BMC and BIOS are suitable for configuring a Flash, and communicate with the Flash through the SPI interface. The CPLD is mainly responsible for the basic functions of PFR through the SPI interface, the three major functions of Detection, Protection and Recovery. If the BMC or BIOS adds additional functions, resulting in insufficient Flash space, usually the number of Flash will be increased for expansion. Since the PFR firmware provided by Intel does not include an expansion mechanism, BIOS and BMC need to develop additional firmware to control more than two Flash. At the same time, the CPLD PFR function also needs to cooperate with BIOS and BMC at the same time.

[0049] Please refer to figure 1 , this embodiment provides a PFR flash memory expansion device, including:

[0050] A programmable logic device, a paging channel and a baseboard management controller, the paging channel is used to transmit instructions of ...

Embodiment 2

[0056] This embodiment provides a PFR flash memory expansion device, including:

[0057] A programmable logic device, a paging channel and a baseboard management controller, the paging channel is used to transmit instructions of the BIOS in the CPU. The paging channel is connected to the programmable logic device through the SPI first signal link, and the programmable logic device is respectively connected to the first flash memory, the second flash memory and the third flash memory through the SPI first signal link; the paging channel The first flash memory, the second flash memory and the third flash memory are respectively connected to the first flash memory, the second flash memory and the third flash memory through the second signal link of SPI; the baseboard management controller is connected to the programmable logic device through the first signal link of SPI, and the programmable logic device is The first signal link is respectively connected to the fourth flash memor...

Embodiment 3

[0061] Please refer to figure 2 , the present embodiment provides a PFR flash memory expansion method, comprising the following steps:

[0062] S1. The programmable logic device receives the SPI_CSO signal sent by the server management device and decodes the SPI_CSO signal.

[0063] The SPI Slave module of CPLD receives the SPI_CSO signal sent by BMC or BIOS, and decodes the received SPI_CSO signal according to the SPI protocol standard.

[0064] S2. Analyze the target flash memory from the decoded SPI_CSO signal.

[0065] The Address decoder module parses the SPI_CSO signal and obtains the source server management device information (BMC or BIOS), searches for all flash memories connected to the source server management device according to the source server management device information as candidate objects; selects the target flash memory from the candidate objects memory as the target flash memory. Obtain the memory required by the task from the analyzed SPI_CSO signal;...

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PUM

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Abstract

The invention provides a PFR flash memory expansion device and method. The device comprises a server management device and a programmable logic device; the server management device is connected with the programmable logic device through the SPI first signal link, and the programmable logic device is connected with the plurality of flash memories through the SPI first signal link; and the server management device is connected with the plurality of flash memories through the SPI second signal link. The flash memory can be expanded for the PFR platform under the condition that firmware is not added, so that BIOS and BMC development customization functions are supported, and the user experience of the PFR platform is improved.

Description

technical field [0001] The invention belongs to the technical field of servers, and in particular relates to a PFR flash memory expansion device and method. Background technique [0002] PFR is a security technology designed by Intel to support the security requirements of the NIST SP 800-193 document. The purpose of PFR is to protect platform assets, detect malicious or wrong behavior such as damaged firmware, and restore platform firmware to a good state. . PFR uses a CPLD as the core of the entire PFR technology, and defines a special pre-start state T-1 (Tminus 1). After the system is powered on, it first enters the T-1 stage. At this time, all other firmware (PCH, CPU, ME, BMC, etc.) , BIOS FLASH for verification. If the verification fails, the PFR CPLD will erase the FLASH area where the verification failed, and use the image file to restore the FLASH data. If the verification is successful, it will enter the normal startup mode of Bootguard, and then T0 mode. In T...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/02H04W68/02
CPCG06F12/0246H04W68/02Y02D10/00
Inventor 谢武志
Owner SUZHOU LANGCHAO INTELLIGENT TECH CO LTD
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