SPI-based single-channel multi-service parallel processing method and chip

Abstract

The invention relates to the technical field of service processing. The embodiment of the invention provides an SPI-based single-channel multi-service parallel processing method and a chip. The SPI-based single-channel multi-service parallel processing method comprises the following steps: caching data acquired from an SPI channel to a first random access memory of SPI equipment, and transferring the data in the first random access memory to a second random access memory of the SPI equipment by adopting a data receiving thread; processing the data in the second random access memory by adopting a service processing thread, and storing a processing result into the second random access memory; transferring the processing result in the second random access memory to the first random access memory by adopting a data sending thread; and enabling the data receiving thread, the business processing thread and the data sending thread to be in a parallel relationship. According to the implementation mode provided by the invention, the response speed and the processing efficiency of the system of the SPI interface to the data received from the SPI interface are improved.

Description

technical field [0001] The invention relates to the technical field of service processing, in particular to an SPI-based single-channel multi-service parallel processing method and a chip using an SPI interface. Background technique [0002] The continuous improvement of memory capacity, CPU processing capacity, and technological level of chips with SPI interface has gradually met the needs of business integration. In the existing solution, according to different services, the SPI chip sets different command lists. The SPI chip does not limit the content of the command list, allowing multiple lists to use the same command. The SPI chip executes the commands in the list in order of receipt . [0003] figure 1 It schematically shows a schematic diagram of the multi-service processing flow of the SPI chip according to the prior art. Such as figure 1 As shown, the internal communication mode of the current SPI chip is a serial mode, which is easy to cause communication block...

AI Technical Summary

Problems solved by technology

like figure 1 As shown, the internal communication mode of the current SPI chip is serial, which is easy to cause communication blockage. At the same time, the chip core uses a single-task operating system, and the instruction processing efficiency is also low.

Even if the chip uses a multi-tasking operating system to process instructions in parallel, it will not be able to improve the processing efficiency of the entire chip due to communication blocking.

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