CT detector AD array synchronous acquisition method

Abstract

The invention discloses a CT detector AD array synchronous acquisition method. According to the method, an SCK main clock is included and outputs a signal to drive an AD array, the SCK main clock generates a plurality of clocks with the same frequency and different phases through a PLL in a chip, and each channel acquires an input signal by using a respective locked clock, carries out clock domain crossing on the acquired data, and unifies in the SCK main clock domain forsubsequent processing. According to the invention, a sampling window of each input data line can be automatically found, and the limitation of basic manufacturing and layout wiring is reduced, so that one FPGA can drive more AD, the cost can be reduced, the information of interaction between every two FPGAs can be reduced, and the stability of a system is improved.

Description

technical field [0001] The invention relates to the technical field of tomographic scanning medical equipment, and more specifically relates to a method for synchronous acquisition of an AD array of a CT detector. Background technique [0002] Among AD chips suitable for CT detectors, the data readout interface of a type of AD chip is an SPI interface. An SPI interface usually has 4 signal lines. In a detector, hundreds of the same ADs are required to form a whole column. These ADs all need FPGAs to control them and collect data. How to use as few FPGAs as possible to control more ADs can not only reduce the cost, but also reduce the information exchanged between FPGAs and improve the stability of the system. There are two ways of hardware connection between FPGA and AD array to deal with this problem in the prior art, one such as figure 1 As shown in , the pins of each AD chip correspond to the pins of the FPGA one by one. The advantage of this is that the SCK and SDO of...

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Problems solved by technology

For example, the SCK1 generated by the FPGA drives AD#1 to output data at the rising edge, and the FPGA can use the falling edge of SCK1 to collect data. However, this solution occupies a large number of FPGA pins, which limits the ability of an FPGA to drive more ADs.

[0003] another such as figure 2 connection with figure 1 In comparison, the number of FPGA pins consumed is greatly reduced, but because the path lengths from FPGA.SCK to AD#1.SCK and to AD#n.SCK are inconsistent (CS_N, SDI signals are the same), AD#1.SDO to AD#1.SCK The path lengths from FPGA.SDO1 and AD#n.SDO to FPGA.SDOn are inconsistent, which causes the delays of all FPGA input pins SDO1, SDO2...SDOn to the same FPGA output pin SCK to be inconsistent. At this time, use the same A SCK sampling all input data may not find a suitable sampling window, such as image 3 shown

In order to solve this problem, the existing method is to require all the above-mentioned connections to be of the same length when wiring the circuit board, but this is limited by the space layout and wiring of the circuit board in actual operation. More AD capabilities

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