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Design method and device of coefficient-configurable digital filter

A technology of digital filter and design method, applied in the direction of digital technology network, impedance network, electrical components, etc., can solve the problems of high resource overhead of multipliers, influence of chip area, etc., and achieve the effect of saving cost and reducing area

Pending Publication Date: 2021-11-26
ASR MICROELECTRONICS CO LTD
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

figure 1 The disadvantage of the FIR digital filter shown is that when implemented by hardware, the resource overhead of the corresponding multiplier is relatively large, which has an impact on the chip area

Method used

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  • Design method and device of coefficient-configurable digital filter
  • Design method and device of coefficient-configurable digital filter
  • Design method and device of coefficient-configurable digital filter

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Embodiment Construction

[0024] see figure 2 , a kind of coefficient configurable digital filter design method that saves digital filter multiplier resources that the application proposes comprises the following steps.

[0025]Step S1: Determine the order of the filter; this refers to clarifying the working scenarios of the digital filter and the design indicators in all scenarios, traversing to obtain the floating point coefficients corresponding to the digital filters in all scenarios, and obtaining the corresponding digital filters in all scenarios The order of the filter, and the largest order is used as the final order of the digital filter.

[0026] Step S2: Determine the quantization bit width of the filter coefficient; this refers to obtaining the quantization bit width that satisfies the minimum filter coefficient in different scenarios according to the filter design indicators in different scenarios, and then satisfies the filter design indicator requirements in all scenarios The maximum v...

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Abstract

The invention discloses a design method of a coefficient-configurable digital filter. The method comprises the following steps: S1, determining the order of a filter; S2, determining the quantization bit width of the filter coefficient; S3, based on the quantization bit width of the filter coefficient obtained in the step S2, carrying out fixed-point processing on the floating-point coefficient of the digital filter generated in the step S1, and calculating final coefficients of the filter in different scenes; and S4, comparing the filter coefficients in different scenes obtained in the step S3, and taking the bit width corresponding to the maximum value of the filter coefficients of the same filter coefficient subscript in different scenes as the coefficient bit width corresponding to the coefficient subscript of the filter. According to the invention, the overhead of multiplier resources is reduced when the digital filter is realized by hardware.

Description

technical field [0001] The present application relates to a design method of a digital filter. Background technique [0002] Digital filter is one of the core parts of digital signal processing, which is widely used in digital communication, image processing, artificial intelligence and other fields. Structurally, digital filters are generally composed of digital multipliers, adders and delayers. In the field of chip design, due to the consideration of chip area, the optimization of multiplier resources has become the focus of current digital filter implementation and research. Many methods have been proposed to optimize the multiplier resources of digital filters. For example, using the symmetry of FIR (Finite Impulse Response, finite impulse response) filter coefficients, engineering uses a symmetrical structure to achieve, which can reduce the number of multipliers by nearly half; for example, for digital filters with fixed coefficients, engineering The multiplier is r...

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Application Information

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IPC IPC(8): H03H17/02
CPCH03H17/0225H03H2017/0081
Inventor 陈政檀甲甲朱学庆
Owner ASR MICROELECTRONICS CO LTD