Analog-to-digital converting system and method with offset and bit-weighting correction mechanisms

Abstract

An analog-to-digital converting system and a method with offset correction mechanisms are disclosed. The method includes steps of: obtaining a direct current offset of an output voltage of a digital analog conversion unit in a system; obtaining first capacitance weights and second capacitance weights sequentially from small to large; subtracting the direct current offset from a digital signal; and multiplying bit values of the digital signal respectively by the corresponding first capacitance weight value or second capacitance weight value to output a decode signal.

Description

technical field [0001] The invention relates to an analog-to-digital conversion system and method, in particular to an analog-to-digital conversion system and method with an offset and bit weight correction mechanism. Background technique [0002] With the rapid development of the information industry, analog-to-digital converters (ADCs) are widely used in voltage conversion. A digital-to-analog conversion unit (DAC) in a commonly used analog-to-digital converter has a segmented capacitor array structure. In a typical two-stage structure, the main components are m most significant bit (MSB) capacitors, n least significant bit (LSB) capacitors, and bridge capacitors. The attenuation coefficient (z) is the sum of the capacitance values ​​of all n least significant bits (LSB) divided by the capacitance value of the bridge capacitor. This coefficient is a value greater than 1; and the impact of the most significant bit on the DAC output voltage (vdac) will be determined Enlarg...

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Problems solved by technology

[0003] However, during circuit layout, the running lines connected to nodes will generate parasitic capacitance, and under the influence of process variation, the capacitance value of each capacitor will be different from the expected value.

Because the equivalent value of the MSB capacitor will be amplified by z times, the change of its capacitance value will also be amplified by z times. Compared with the LSB capacitor, its small error is enough to cause the output voltage of the analog-to-digital converter to produce periodic abnormal Linearity shift, resulting in reduced accuracy of voltage conversion

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