Clock duty ratio correction circuit shared by multiple paths

Abstract

The invention relates to the field of clock duty ratio calibration, and discloses a multi-channel shared clock duty ratio correction circuit, which comprises a plurality of main alternating current coupling buffers, a multiplexer, a shared resistor string and a copy bias module, each main alternating current coupling buffer is connected with the multiplexer through a bias resistor, and the multiplexer is connected with the copy bias module through the shared resistor string. The clock duty ratio correction circuit shared by multiple paths has the advantages that the area can be saved, the duty ratio correction precision is high, and the noise is low.

Description

technical field [0001] The invention relates to the field of clock duty ratio calibration, in particular to a clock duty ratio correction circuit shared by multiple channels. Background technique [0002] Duty cycle correction requires precision but is larger in area. When multiple clocks are used to correct the duty cycle, such as clock0, clock90, clock180 and clk270, the occupied area is large. figure 1 is a schematic diagram of a conventional duty cycle correction (clock duty cycle correction (DCC)) scheme, figure 1 Specifically, the clock duty cycle correction based on variable PMOS / NMOS width, in this method, the width of PMOS (MP1) and NMOS (MN1) in the inverter can be programmed, and the inverter can be used in the clock chain When using a phaser, the duty cycle is changed by adjusting the strength of PMOS and NMOS. Assuming that PMOS has 10 widths and NMOS has 10 widths, when PMOS is turned on for 5 widths and NMOS is turned on for 5 widths, the strengths of PMOS ...

AI Technical Summary

Problems solved by technology

The main disadvantage is that the current sources ISR1 / ISR2 will generate additional noise, and when the current sources need to be well matched, a large area is required to reduce the matching mismatch

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