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Method and circuit for accessing write data path of on-chip memory control unit

A control unit and storage control technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of no data flow control, DAG data damage, poor reliability, etc., to reduce the bit error rate and packet loss rate, and ensure normal use. , the effect of ensuring integrity

Active Publication Date: 2022-02-01
声龙(新加坡)私人有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, the existing solutions have the following problems: 1) There is no data flow control for writing data path, there is the possibility of packet loss and bit error, and the reliability is poor; 2) The control right of writing data path cannot be flexibly configured; 3) If If the storage unit has a damaged area, the stored DAG data will be damaged, which will increase the error rate and reduce the computing power of the computing chip.

Method used

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  • Method and circuit for accessing write data path of on-chip memory control unit
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  • Method and circuit for accessing write data path of on-chip memory control unit

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Embodiment Construction

[0050] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0051] In order to facilitate the understanding of the embodiments, the relevant terms are first explained:

[0052] 1) DAG (Direct Acyclic Graph) directed acyclic graph technology.

[0053] In order to facilitate the understanding of the embodiment of the present application, a circuit for accessing a write data path of an on-chip storage control unit based on which the embodiment of the present application is based is firstly described below.

[0054] Such as figure 1 As shown, the embodiment of the present invention provides...

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Abstract

The invention discloses a method and circuit for accessing a write data path of an on-chip storage control unit. The method comprises that: a target controller sends a write address and write data to a write data path interface; the write data path interface sends a write address and write data to the address conversion unit; the address conversion unit sends the target address and the write data to a plurality of storage control units, and determines a target storage control unit; the address conversion unit obtains a feedback signal of the target storage control unit and sends the feedback signal to the target controller; and if the feedback signal is writable, the target controller sends a write signal to the target storage control unit, and the target storage control unit stores the write data after receiving the write signal. According to the technical scheme, data transmission is controlled through the data flow between the write data path interface and the target controller, the bit error rate and the packet loss rate can be reduced, and the reliability of write operation is improved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a method and a circuit for accessing a writing data path of an on-chip storage control unit. Background technique [0002] DAG (Direct Acyclic Graph) directed acyclic graph technology is widely used in the blockchain field, especially in the proof-of-work algorithm. DAG is the encrypted information of all blocks on the blockchain, and its volume gradually increases with the development of the blockchain. The workload proves the chip, and the data that the calculation depends on is the DAG file. Therefore, before computing on the chip, it is first necessary to write the DAG into the memory space of the chip. In order to solve the above technical problems, in the existing technical solution, the host computer sends the entire DAG to the computing chip through a high-speed bus. While receiving data, the computing chip completes protocol analysis internally...

Claims

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Application Information

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IPC IPC(8): G06F13/16G06F13/40
CPCG06F13/1668G06F13/404G06F13/4022G06F13/1642
Inventor 张雨生田佩佳蔡凯
Owner 声龙(新加坡)私人有限公司
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