Duty ratio adjusting circuit of clock signal, chip and duty ratio adjusting method

Abstract

The invention provides a duty ratio adjusting circuit of a clock signal, a chip and a duty ratio adjusting method. The circuit comprises a decoding module and a duty ratio adjusting module, and the decoding module receives a configuration signal and generates a control signal based on the configuration signal; and the duty ratio adjusting module is connected with the decoding module and receives the clock signal, and the duty ratio adjusting module delays the rising edge or the falling edge of the received clock signal by at least one stepping value based on the control signal so as to generate an adjusted clock signal. In the duty ratio adjusting circuit, the input and the output of the duty ratio adjusting circuit are analog signals, so that the stepping of the duty ratio adjusting circuit can be smaller, and the stepping linearity of the duty ratio adjusting circuit is better; and the stepping of the duty ratio adjusting circuit changes little along with the working voltage, the temperature and the process angle, and particularly, the duty ratio adjusting circuit is a very good choice when the duty ratio of a high-speed clock path needs to be adjusted on the large-size process.

Description

technical field [0001] The invention relates to the technical field of clock signal adjustment, in particular to a clock signal duty ratio adjustment circuit, a chip and a duty ratio adjustment method. Background technique [0002] In the design of high-speed DRAM products, in order to meet the problem of chip speed, it is necessary to place a delay line on the clock path to adjust the duty cycle of the input clock. With the upgrade of the DRAM product interface, the input clock speed is getting higher and higher, and the linearity requirements for the delay line step are also getting higher and higher. At the same time, it is required that the delay line step change with PVT as small as possible. [0003] At present, digital delay lines are generally used in high-speed DRAM products to complete the adjustment of the clock duty cycle. The working principle of the digital delay line is mainly to change the slope of the rising and falling edges of the clock signal by adding a...

AI Technical Summary

Problems solved by technology

The working principle of the digital delay line is mainly to change the slope of the rising and falling edges of the clock signal by adding a capacitive load behind the inverter, thereby affecting the transmission delay of the clock signal

With the change of operating voltage, temperature and process, the step of this digital delay line changes greatly, and the linearity is relatively poor

Especially in some larger-sized crafts, it becomes very difficult to adjust the training or duty cycle through the digital delay line

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