Integrated circuit device with multiple stacked dies

Abstract

An integrated circuit device having a plurality of stacked dies is described. The integrated circuit device includes a first die of the plurality of stacked dies, the first die having input / output elements configured to receive an input signal, the first die including a signal driving circuit and a chip selection circuit, the signal driving circuit is configured to provide an input signal for each bare chip in the plurality of stacked bare chips, and the chip selection circuit is used for generating a plurality of chip selection signals for the plurality of stacked bare chips; a second die of the plurality of stacked dies is coupled to the first die, the second die having a functional block configured to receive an input signal; wherein the second die receives the input signal, and the input signal is received in response to a chip selection signal, corresponding to the second die, in a plurality of chip selection signals. A method of implementing an integrated circuit device having a plurality of stacked dies is also described herein.

Description

technical field [0001] The present invention relates generally to integrated circuit devices, and in particular to integrated circuit devices having a plurality of stacked dies and methods of implementing integrated circuit devices having a plurality of stacked dies. Background technique [0002] The implementation of integrated circuit devices is constantly changing as the size, power, and performance of integrated circuit devices decrease. Different types of integrated circuit devices may include multiple die, also commonly referred to as chips. Integrated circuit devices with multiple dies are often referred to as 3D integrated circuit devices. Some 3D integrated circuit devices with multiple die may include an interposer and are often referred to as devices implementing stacked silicon interconnect technology (SSIT). For example, multiple die can be placed individually on the surface of the interposer instead of being stacked on top of each other. Microbumps and throu...

AI Technical Summary

Problems solved by technology

[0003] While the stacking of die in a stacked integrated circuit device increases the logic capacity of the integrated circuit device, it also reduces the die edge width and the die surface area that has the potential to be accessed by contacts on the integrated circuit device itself The contact pads of the die themselves

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