Time delay circuit and time delay structure

Abstract

The invention provides a time delay circuit and a time delay structure. The circuit comprises a first delay unit which is used for delaying a rising edge and / or a falling edge of a pulse signal, an input end of which receives the pulse signal and an output end of which outputs a first delay signal, and a second delay unit which is used for delaying the first delay signal, an input end of which is connected to the output end of the first delay unit and an output end of which is connected to the output end of the second delay unit. The output end outputs a second delay signal, the delay time between the rising edge of the second delay signal and the rising edge of the pulse signal is recorded as the rising edge delay time, and the delay time between the falling edge of the second delay signal and the falling edge of the pulse signal is recorded as the falling edge delay time; the change value of the rising edge delay time and / or the falling edge delay time along with the change of the first parameter is within a first range, and the first parameter comprises at least one of the manufacturing process, the power supply voltage wave and the working temperature of the time delay circuit.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, in particular to a delay circuit and a delay structure. Background technique [0002] At present, a delay circuit is often used in semiconductor components, and the delay circuit is a circuit capable of delaying a pulse signal for a certain time. figure 1 It is a schematic diagram of an input signal and an output signal passing through a delay circuit. After the input signal passes through the delay circuit, a delayed signal is output, such as figure 1 As shown, the output signal is the signal after the delay time T of the input signal. figure 1 What is shown is the case where both the rising edge and the falling edge of the input signal are delayed by time T, and there is another case where only the rising edge of the input signal is delayed by time T or only the falling edge of the input signal is delayed by time T. [0003] In the existing time-delay circuit, the time-d...

AI Technical Summary

Problems solved by technology

[0003] In the existing time-delay circuit, the time-delay T of the output signal through the time-delay circuit will greatly change (increase or decrease) with changes in parameters such as power supply voltage, operating temperature and manufacturing process, which will affect the delay time. performance of the circuit

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