Distributed storage interconnection structure of graphics processor, graphics card and memory access method

Abstract

The invention discloses a distributed storage interconnection structure of a graphics processor, a graphics card and a memory access method, and the structure comprises a video processing unit, a memory access unit and a memory access unit, sending the video processing memory access operation command to a direct memory access controller through a direct memory access path; the direct memory access address range is a low-latency memory access demand address range; each graphic processing unit is used for sending a graphic processing memory access operation command with a high-bandwidth memory access requirement to the full-interconnection centralized memory access arbitration unit; and the centralized memory access arbitration unit is used for performing centralized arbitration according to the graphic processing memory access operation command to obtain a graphic processing memory access path, and sending the graphic processing memory access operation command to the corresponding memory controller through the graphic processing memory access path. According to the invention, a structure combining direct memory access and centralized memory access is adopted, and the low-delay requirement of video processing and the high-bandwidth requirement of graphic processing are met at the same time.

Description

technical field [0001] The present invention relates to the technical field of graphic processors, in particular to a distributed storage interconnection structure of a graphic processor, a graphics card and a memory access method. Background technique [0002] This section is intended to provide a background or context to embodiments of the invention that are recited in the claims. The descriptions herein are not admitted to be prior art by inclusion in this section. [0003] The composition of discrete graphics SoC chips has become more and more complex in recent years. It not only includes traditional graphics processing subsystems (graphics processing subunits or graphics processing cores, supporting various graphics rendering), but also gradually adds multi-standard video processing. (codec) system, high-performance computing subsystem, audio and video output subsystem, etc. Among them, due to the large number of graphics processing cores in the graphics rendering par...

AI Technical Summary

Problems solved by technology

[0005] Due to the structural characteristics of the memory interconnection, that is, all processing subsystems need to aggregate the memory access requirements to the fully interconnected structure in the center of the chip, and then distribute them to the memory controller on the periphery of the chip. The delay of all memory access operations is very large. Latency characteristics are acceptable for graphics processing subsystems, but often have adverse effects on other subsystems (sub-processing units) in the chip, such as video processing subsystems

Regarding the design of the video processing core, due to the cost of area power consumption, it is often difficult to support the external memory access environment with a particularly large delay

If the delay exceeds a design tolerance, the internal processing pipeline will enter the waiting state after processing the internal data. At this time, the performance of video processing (the number of frames with a certain resolution processed per second) will be as the external delay increases and decreases linearly

Therefore, in a system with a GPU with a large access bandwidth and delay, the final video processing performance that can be obtained is often relatively poor.

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