Buried gate transistor, manufacturing method thereof and semiconductor memory device

Abstract

The invention discloses a buried gate transistor, a manufacturing method thereof and a semiconductor memory device, relates to the technical field of semiconductor manufacturing, and aims to improve the performance of the semiconductor memory device. The buried gate transistor is applied to a semiconductor memory device, and comprises a semiconductor substrate; a gate trench in the substrate; the gate dielectric layer is positioned on the inner wall of the gate trench; the gate conductor layer is located in the lower portion of the gate groove and comprises a barrier layer and a gate metal layer, and the top of the barrier layer is lower than the top of the gate metal layer; and a cap layer on the gate conductor layer; wherein an air side wall is formed between the top surface of the barrier layer and the bottom surface of the cover layer. The buried gate transistor, the manufacturing method thereof and the semiconductor memory device provided by the invention are used for manufacturing the semiconductor memory device.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a buried gate transistor, a manufacturing method thereof, and a semiconductor storage device. Background technique [0002] In the process of manufacturing a buried-gate transistor applied to a semiconductor memory device, a gate metal layer is usually buried in a substrate of the transistor. [0003] During the operation of the semiconductor memory device, a parasitic capacitance is formed between the gate metal layer and the active contact. As the integration density of unit devices increases, the existence of these parasitic capacitances will cause a problem of resistance-capacitance delay (RC Delay), thereby affecting the performance of semiconductor memory devices. Contents of the invention [0004] The object of the present invention is to provide a buried gate transistor, its manufacturing method, and a semiconductor storage device, so as to improve ...

AI Technical Summary

Problems solved by technology

As the integration density of unit devices increases, the existence of these parasitic capacitances will cause the problem of RC Delay, which will affect the performance of semiconductor memory devices

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