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Semiconductor memory device

A semiconductor and memory technology, applied in the field of three-dimensional semiconductor memory devices, can solve the problems of increased integration density and limitations of two-dimensional semiconductor devices

Pending Publication Date: 2022-03-29
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since miniaturization of patterns requires extremely expensive equipment, the integration density of two-dimensional semiconductor devices has increased, but is still limited

Method used

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  • Semiconductor memory device
  • Semiconductor memory device
  • Semiconductor memory device

Examples

Experimental program
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Embodiment Construction

[0025] figure 1 is a simplified circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to at least one example embodiment.

[0026] refer to figure 1 , the cell array CA of the 3D semiconductor memory device according to at least one example embodiment may include a plurality of sub-cell arrays SCA, but example embodiments are not limited thereto. The sub-cell array SCA may be arranged along the second direction D2 of the cell array CA, but is not limited thereto. According to some example embodiments, a 3D semiconductor memory device may include a plurality of cell arrays CA, but example embodiments are not limited thereto.

[0027] Each of the sub-cell arrays SCA may include a plurality of bit lines BL, a plurality of word lines WL, and / or a plurality of memory cell transistors MCT, and the like. One memory cell transistor MCT may be included between one word line WL and one bit line BL (for example, arranged between on...

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PUM

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Abstract

A semiconductor memory device is disclosed. The semiconductor memory device may include: at least one semiconductor pattern including a horizontal portion extending in a second direction parallel to a top surface of a semiconductor substrate and a vertical portion extending in a first direction; at least one gate electrode on a horizontal portion of the at least one semiconductor pattern and extending in a third direction different from the first direction and the second direction; and at least one information storage element connected to the vertical portion of the at least one semiconductor pattern, in which a thickness of the horizontal portion of the at least one semiconductor pattern in the first direction is smaller than a thickness of the vertical portion of the at least one semiconductor pattern in the first direction.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0124385 filed with the Korean Intellectual Property Office on September 25, 2020, the entire contents of which are hereby incorporated by reference. technical field [0002] Various example embodiments of inventive concepts relate to a semiconductor memory device and / or a method of operating a semiconductor memory device, and more particularly, to a three-dimensional (3D) semiconductor memory device having improved electrical characteristics and / or to operating a 3D semiconductor memory device. Method for memory device. Background technique [0003] In order to meet consumer demands for superior performance and inexpensive price, it is desired to increase the integration density of semiconductor devices. In a semiconductor device, since its integration density is an important factor in determining the price of a product, increased integration density is particularly desired and / or...

Claims

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Application Information

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IPC IPC(8): H01L27/108H01L27/22H01L27/24
CPCH10B63/30H10B61/22H10B63/84H10B12/30G11C5/063H10B12/03H10B12/05H10B12/488H10B12/482H10B12/50H10B12/33
Inventor 朴宰弘朴在花金汶根黄定夏
Owner SAMSUNG ELECTRONICS CO LTD
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