Preparation method of semiconductor device and semiconductor device

Abstract

The invention discloses a preparation method of a semiconductor device and the semiconductor device, and the preparation method comprises the steps: providing a substrate, forming a stacking layer on the substrate, forming a channel structure which penetrates through the stacking layer along a first direction and extends into the substrate, the channel structure comprises a channel layer and a storage layer surrounding the channel layer, removing the substrate so as to expose a part of the storage layer of the channel structure, removing the exposed part of the storage layer so as to expose a part of the channel layer to form a channel layer external connection part, and removing the external connection part of the channel layer. And forming a common source layer located on the first surface of the stack layer, wherein the common source layer is connected with the external connection part of the channel layer. Therefore, the preparation method can replace SEG and IMP processes, the process difficulty is lower, and the cost is lower. The preparation method is not limited by the number of the stacked layers, so that the number of the stacked layers can be further increased.

Description

technical field [0001] The present invention generally relates to electronic devices, and more particularly, to a semiconductor device and a method of manufacturing the same. Background technique [0002] The traditional 2D NAND memory has reached the storage limit. On this basis, in order to seek new breakthroughs, 3D NAND developed vertically has emerged. How to increase the storage capacity per unit area of ​​3D NAND is a problem that needs to be solved. The current practice It is to increase the number of effective gate layers and insulating layers in the vertical direction on the premise that the thickness of each insulating layer and gate layer remains unchanged. [0003] In a framework of 3D NAND, in the formation process of the storage channel structure (Cell loop), the process of the channel hole (CH loop process) adopts the formation of a silicon epitaxial layer (SEG) at the bottom of the channel hole and ion implantation ( IMP), the channel layer in the channel h...

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Problems solved by technology

[0004] As the 3D NAND stack continues to increase, the SEG formation process and the ion implantation process for the SEG become more and more difficult, making it difficult to electrically connect the channel layer and the common source layer

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