Digital signal generator for reducing audio artifacts

A digital signal and generator technology, applied in audio amplifiers, low-frequency amplifiers, improved amplifiers to reduce noise effects, etc.

Pending Publication Date: 2022-05-06
NXP BV
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AI-Extracted Technical Summary

Problems solved by technology

These artifacts can occur, for example, when an audio amp...
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Method used

[0041] The inventors of the present disclosure have realized that the approximate calculation of the raised cosine function that can be efficiently implemented in digital logic by the combination of a(x-b)2+c functions is referred to as an approximation method from here on. In the first half of the approximate raised cosine, a is positive and in the second half of the raised cosine, a is negative. The coefficients b and c are chosen such that the two half-curves fit together exactly, thereby ensuring that the curves are continuous. The derivative of a(x-b)2+c is y=2ax-2ba, a and b depending on the operand area. Therefore, the derivative of the approximation looks like a triangle wave. Thus, by using the counter 110 and the integrator 114, the ...
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Abstract

A digital signal generator apparatus and method are described. The digital signal generator comprises a counter, an integrator and a comparator. The counter incrementally counts or incrementally counts from an initial counter value depending on a counter control input. The comparator has a first input coupled to a counter output, a threshold input, and a comparator output coupled to the counter control input. The integrator has an input coupled to the counter output and an output coupled to a digital signal generator output. The digital signal generator determines a counting direction following an initial direction depending on a comparison between a threshold applied to the threshold input and a counter output value. The digital signal generator may implement an approximate waveform generation with a raised cosine function. The generated waveform may be used to reduce audio artifacts in an audio amplifier during muting operation or canceling muting operation, or during power-on, power-off operation.

Application Domain

Amplifier modifications to reduce noise influenceGain control +3

Technology Topic

IntegratorAudio frequency +3

Image

  • Digital signal generator for reducing audio artifacts
  • Digital signal generator for reducing audio artifacts
  • Digital signal generator for reducing audio artifacts

Examples

  • Experimental program(1)

Example Embodiment

[0032] figure 1 An audio amplifier system 100 including a digital signal generator 120 is shown according to an embodiment. The audio amplifier system 100 may also include a digital-to-analog converter (DAC) 122 , an amplifier stage 126 , which may be, for example, a class A, AB, or D amplifier, and a speaker 130 .
[0033] The digital signal generator 120 may include a controller 112 , an integrator 114 , a counter module 110 and a comparator 108 . Controller 112 may have reset output 102 coupled to counter module 110 and integrator 114 . Controller 112 may have an input connected to counter output 116 . Counter output 116 may be connected to a first input of comparator 108 and an input of integrator 114 . Controller 112 may have threshold output 106 connected to a second input of comparator 108 . Comparator output 104 may be connected to up and down control inputs of counter module 110 . The output of integrator 114 may be connected to digital signal generator output 118 . Digital signal 120 may be implemented entirely using hardware digital logic gates. In other examples, one or more of counter module 110, integrator 114, controller 112, and comparator 108 may be implemented as software running on a microprocessor.
[0034] In operation, digital signal generator output 118 may be connected to an input of DAC 122 . DAC 122 may be omitted if amplifier stage 126 is a digital amplifier or has a digital amplifier input. Amplifier stage 126 may have an audio input 124 connected to the output of DAC 122 . Amplifier stage output 128 may be connected to speaker 130 .
[0035] Figure 2A An example method 150 of operation of the audio amplifier system 100 is shown. At step 152, the audio amplifier 100 may be switched on or unmuted. At step 154, digital signal generator 120 may generate an increased raised cosine approximation signal. At step 156 , the raised cosine approximation signal may be applied to the audio input of amplifier stage 126 . Following step 156 , audio amplifier stage 126 may then receive the desired audio signal based on audio input 124 . like figure 1 The DAC output is connected directly to the audio input 124 as shown. In other embodiments where amplifier stage 126 is a digital amplifier, DAC 122 may be omitted, and digital signal generator output 118 may be digitally combined with audio input 124, eg, using a multiplexer or other digital logic.
[0036] Figure 2B An example method 160 of operation of the audio amplifier system 100 is shown. At step 162, the audio amplifier 100 may be turned off or muted. At step 164, the digital signal generator 120 may generate a reduced raised cosine approximation signal. At step 166 , the raised cosine approximation signal may be applied to the audio input of amplifier stage 126 .
[0037] Figure 3AA method 200 of generating an approximate raised cosine signal that can be increased or decreased is shown. Method 200 may be implemented, for example, using digital signal generator 120 . At step 202, a counter threshold may be set, eg, by the controller 112 based on the threshold output 106 setpoint. At step 204, the counter 110 and the integrator 114 may be reset by the controller 112 to respective initial values. In some examples, the order of steps 202 and 204 may be reversed. An integrator reset value can be set to determine the DC voltage level. The counter reset value could eg be zero, but could be some other value. At step 206, the counter 110 may count up or down from the initial counter value determined by reset. The initial counter direction may be determined depending on whether an increasing raised cosine approximation or a decreasing raised cosine approximation is required. The counter will initially count up for an increasing raised cosine approximation, and the counter 110 will initially count down for a decreasing raised cosine approximation. After step 206, the method proceeds to step 210 where a comparison between a threshold value and a counter value is made. In the digital signal generator 120 this can be done eg by the comparator 108 comparing the threshold value set by the controller 112 with the current counter value based on the counter output 116 . If the threshold has not been reached, the method proceeds to step 208 and the counter continues counting in the same direction as previously set. The method then returns to 210 to repeat the check against the threshold. If the threshold has been reached, the method proceeds to 212 and the counting direction is changed. The method 200 then proceeds to step 214 where a check is made as to whether the initial counter value set at step 204 has been reached. If the initial counter value has not been reached, the method proceeds to step 216 and counting continues in the same direction. After step 216 the method then returns to the check at 214 . If at step 214 the initial counter value has been reached, the method proceeds to step 218 and the process ends.
[0038] Figure 3B A graph 260 shows the counter value on the y-axis versus time on the x-axis. Graph 260 shows an example of counter output value 262 and integrator output 264 of digital signal generator 120 when method 200 is implemented to generate an increased cosine approximation signal. The counter 120 outputs a sawtooth waveform or a triangular waveform that increases from an initial counter value to a threshold value and then decreases from the threshold value to the initial value. Integration of this waveform by integrator 114 produces an increasing approximation of the raised cosine.
[0039] Figure 3C A graph 270 is shown of the counter value on the y-axis versus time on the x-axis. Graph 270 shows an example of counter output value 272 and integrator output 274 of digital signal generator 120 when method 200 is implemented to generate a reduced cosine approximation signal. The counter 120 outputs a sawtooth waveform that decreases from an initial value to a threshold and then increases from the threshold to an initial value. Integration of this waveform by integrator 114 produces an increasing approximation of the raised cosine.
[0040] In order to implement raised cosine (or cosine in general), a lookup table (memory) is usually required. The size of this memory depends on the desired resolution. To reduce memory size, it is possible to interpolate between subsequent points, but this either limits accuracy or requires higher order interpolation, which means potentially a lot of hardware.
[0041] The inventors of the present disclosure have realized that the raised cosine function can be obtained by a(x-b) 2 Approximate calculations efficiently implemented in digital logic by combinations of +c functions are referred to as approximation methods from here on. In the first half of the approximate raised cosine, a is positive and in the second half of the raised cosine, a is negative. The coefficients b and c are chosen such that the two half-curves fit together exactly, thereby ensuring that the curves are continuous. a(x-b) 2 The derivative of +c is y=2ax-2ba, a and b depending on the operand area. Therefore, the derivative of the approximation looks like a triangle wave. Thus, by using the counter 110 and the integrator 114, the digital signal generator 120 can generate an approximate cosine that may be less prone to clicks than, for example, a simple linear ramp starting from equal to zero volts DC (or other DC value). Provides improved audio artifact reduction for popping and popping.
[0042] Figure 4A A method of generating the continuous approximate raised cosine signal 300 using, for example, the digital signal generator 120 is shown. At step 302 , a counter threshold may be set by the controller 112 . At step 304, the counter 110 and the integrator 114 may be set to respective initial values. In some examples, the order of steps 302 and 304 may be reversed. The initial values ​​of counter 110 and integrator 114 may be the same or different. At step 306, the counter may begin counting up or down in an initial direction. The method then proceeds to step 310 and a check is made to see if the first threshold has been reached. This check can be done in digital signal generator 120 by comparator 108 comparing counter output 116 to threshold output 106 . If the first threshold has not been reached, the method proceeds to step 308 and counting continues in the same direction, whereupon the method returns to step 310 . Once the first threshold has been reached, the method proceeds to step 312 and the counter direction is changed. After changing direction, a second threshold is set at step 314 . This may be done, for example, by controller 112 setting the second threshold based on threshold output 106 . The method then proceeds to step 318 where a check is made to see if the second threshold has been reached. If the second threshold has not been reached, then at step 316 the counter will continue counting in the same direction as previously defined. The method then returns to step 318. Once the second threshold has been reached, method 300 proceeds to step 320 and changes the counter direction again. At step 322, the controller 112 may set the counter threshold back to the first value. The method then proceeds to 306 where the counter 110 counts up or down, the direction is determined by the current counter direction value and the cycle repeats.
[0043] Figure 4B A graph 330 is shown of the counter value on the y-axis versus time on the x-axis. Graph 330 shows an example of a waveform generated using method 300 . Waveform 332 shows the output of a counter that is generating a continuous triangle wave. Waveform 334 corresponds to the output of integrator 114 which is approximated by integrating the counter output to generate a raised cosine wave.
[0044] Figure 5 A digital signal generator 400 according to an embodiment is shown. Digital signal generator 400 may be implemented using digital logic hardware and may be used to implement methods 200 and 300, for example. The digital signal generator 400 includes a counter 410 , a comparator 408 and an integrator 414 . The integrator 414 includes a summation block 420 , a delay element 430 and a gain block 424 .
[0045] Counter 410 may be configured to count up and count down, and may also include some control logic implemented as a state machine. The counter may have a clock input 402, a preset value input 404, which may be used to determine the counter step size S, for example. The counter 410 may also have a reset input 406 and an up and down control input 412 . Counter output 418 may also be connected to a first input of comparator 408 . A second input 416 of comparator 408 may receive a threshold value from a controller (not shown). The comparator output may be connected to up and down control input 412 . The counter output 418 may be connected to a first input of a summing module 420 . A second input of summation block 420 may be connected to output 426 of delay element 430 . The summation block output 422 may be connected to the input of the delay element 430 and the input of the gain block 424 . The output of gain block 424 may be connected to signal generator output 428 . Reset input 406 ′ may be connected to delay element 430 . Delay element 430, which may be a hardware register, may also be connected to clock input 402 (not shown).
[0046] In operation, digital signal generator 400 may generate the augmented cosine approximation shown in graph 260 in a manner similar to method 200 . On reset, which may be determined by a controller (not shown) connected to reset input 406, the output of the counter may be set to zero. The up and down control input 412 may, for example, be a logic high indicating the direction of counting up, and may set the integrator start value. After reset, every clock cycle, the output of the counter 410 is incremented by S, the step size of the counter, which is determined by the preset value input 404 . At some threshold determined by the threshold, the comparator output 412 goes logic low, and thus the counter 410 goes down counting, then the output of the counter decreases by S every clock cycle until it reaches 0, at which point it will stop. The integrator output corresponding to digital signal generator output 428 will be the integral of the triangular wave generated by counter 410, which will approximate a raised cosine waveform as previously described.
[0047] The approximate raised cosine length and magnitude can be varied by varying the clock frequency of the clock applied to the counter and the counter step value. The approximate raised cosine magnitude can be changed by changing the gain of the gain block 424 . The final amplitude can usually be set to half the supply voltage so that the desired audio signal can have maximum voltage swing in either direction.
[0048] The digital signal generator can also generate repeating triangular waveforms using a second threshold similar to that described for method 300 . In order to be able to reconstruct the full sine wave, the counter 410 may need to be able to count less than zero. In an alternative example, after counter 410 , the correct DC value can be subtracted to avoid runaway integrator 414 . Subsequently, continuous cosine waves can be generated with minor adjustments.
[0049] The digital signal generator 400 allows the use of very simple hardware to create an approximation of cosine or raised cosine. Compared to generating raised cosine (or cosine in general) digitally, a lookup table (memory) is usually required. The size of this memory depends on the desired resolution. To reduce memory size, it is possible to interpolate between subsequent points, but this either limits accuracy or requires higher order interpolation, which also implies a lot of hardware.
[0050] In audio amplifier system 100, digital signal generator 400 may be used instead of digital signal generator 120 to reduce audio artifacts. Using an approximate raised cosine during mute/unmute or power up/down operations may reduce audio artifacts compared to using a linear ramp because the transition from DC (typically 0) to a linear ramp results in a smaller shift in the derivative. Large discontinuities, and therefore more spectral content, resulting in an audible plop.
[0051] A specific application of the approximate cosine function is found in raised cosine start-up of audio amplifiers. Switching the amp from off to on will often cause an audible plop from the speakers. To reduce audio pop, a smoother transition between off and on can be used. Embodiments of the digital signal generator generate an approximation of a continuous raised cosine, since cosine at 0 and pi (pi) have derivatives that are zero. As a result, there are fewer spectral components and the audible plop is greatly reduced. Approximate cosines generated by the described digital signal generator and method can provide audio artifact reduction performance similar to real raised cosine signals, but have significantly reduced area when implemented in hardware logic.
[0052] A digital signal generator apparatus and method are described. The digital signal generator includes a counter, an integrator and a comparator. The counter counts up or down from an initial counter value depending on the counter control input. The comparator has a first input coupled to a counter output, a threshold input, and a comparator output coupled to the counter control input. The integrator has an input coupled to the counter output and an output coupled to the digital signal generator output. The digital signal generator determines a counting direction after an initial direction depending on a comparison between a threshold applied to the threshold input and a counter output value. The digital signal generator may implement waveform generation with an approximation of a raised cosine function. The generated waveforms can be used to reduce audio artifacts in an audio amplifier during mute or unmute operation or during power up, power down operation.
[0053]In some example embodiments, the sets of instructions/method steps described above are implemented as functions and software instructions embodied in a set of executable instructions programmed on a computer or with said executable instructions and controlled by said Implemented on a machine controlled by executable instructions. Such instructions are loaded for execution on a processor (eg, one or more CPUs). The term processor includes microprocessors, microcontrollers, processor modules or subsystems (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor may refer to a single component or multiple components.
[0054] Although the appended claims are directed to specific combinations of features, it is to be understood that the scope of the present disclosure also includes any novel feature or any novel combination of features or combination of said novel features disclosed herein, either explicitly or implicitly. Any generalization, regardless of whether the novel feature relates to the same invention as the invention presently claimed in any claim or whether the novel feature alleviates any or all of the same technical problems as the present invention alleviates.
[0055] Features that are described in the context of separate embodiments can also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination.
[0056] The applicant hereby reminds that during the prosecution of this application or any further application derived therefrom, new claims may be formulated to such features and/or combinations of such features.
[0057] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, and the term "a" or "one" does not exclude a plurality, and a single processor or other unit can fulfill the functions of several components recited in the claims, And reference signs in the claims shall not be construed as limiting the scope of the claims.

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