Method and processing unit for randomly generating instruction sequence
A technology of processing unit and instruction sequence, which is applied in the fields of conditional code generation, machine execution device, register device, etc., which can solve the problems of random test of instruction correctness and reliability, excessive NaN value, etc.
Pending Publication Date: 2022-05-20
ALIBABA GRP HLDG LTD
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Problems solved by technology
However, if there are too many NaN values, the correctness and reliability of the instruction random test will be questioned
Method used
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[0048] The present disclosure is described below based on examples, but the present disclosure is not limited only to these examples. In the following detailed description of the disclosure, some specific details are set forth in detail. The present disclosure can be fully understood by those skilled in the art without the description of these detailed parts. In order to avoid obscuring the essence of the present disclosure, well-known methods, procedures, and procedures are not described in detail. Additionally, the drawings are not necessarily drawn to scale.
[0049] The following terms are used in this document.
[0050] Simulator: It mainly simulates the functions of the hardware processor and the program of the instruction system through software, so that computers or other multimedia platforms (handheld computers, mobile phones) can run software on other platforms.
[0051] Instruction set (instruction set architecture): It is a set of instructions used to calculate ...
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The invention provides a method for randomly generating an instruction sequence and a processing unit. The method comprises the following steps: dividing floating point registers of a to-be-tested processing unit into a plurality of groups, wherein the groups respectively correspond to a plurality of floating point types supported by an instruction set of the to-be-tested processing unit; using a random value to initialize each floating point register according to the floating point type corresponding to the group to which the floating point register belongs; and generating an instruction sequence, and when the floating point instruction is generated, selecting a floating point register from a specific group or a specific group set in the plurality of groups as the operand of the floating point instruction according to the floating point type of the operand specified by the floating point instruction. According to the embodiment of the invention, when the floating point instruction is generated, the floating point register is selected from the specific group or the specific group set as the operand of the floating point instruction according to the specified floating point type, so that no NaN is generated when the generated floating point instruction is executed by the to-be-tested processing unit, and the correctness of random testing of the instruction is ensured.
Description
technical field [0001] Embodiments of the disclosure belong to the field of chip testing, in particular to a method and a processing unit for randomly generating instruction sequences. Background technique [0002] Instruction random testing is an important part of the processor verification process. Instruction random testing refers to generating instruction sequences to test a processing unit. Instruction random testing can greatly reduce the burden of verification engineers writing a large number of test cases during chip verification. At the same time, it can reduce the influence of human factors in the verification process and achieve better test results. [0003] The processing unit is mainly composed of instruction set architecture and microarchitecture. The instruction set architecture supports multiple floating-point types, such as single-precision, multiple-precision, double-precision, and quad-precision floating-point types. The micro-architecture usually uses ...
Claims
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Login to View More IPC IPC(8): G06F9/30
CPCG06F9/3013G06F9/30094
Inventor 刘志伟
Owner ALIBABA GRP HLDG LTD