Interface of memory circuit and memory system thereof

Abstract

The interface of the memory circuit comprises a chip enabling end, at least one data end and a data gating end. The chip enable terminal receives a chip enable signal that can vary between a first high voltage and a low voltage and is used to enable the memory circuit. The at least one data terminal receives at least one first data signal that can vary between a second high voltage and the low voltage. The data strobe terminal receives a first data strobe signal that is periodically variable between a second high voltage and a low voltage. The first data strobe signal is synchronized with at least one first data signal and is configured to latch and sample the at least one first data signal. The first high voltage is higher than the second high voltage, and the second high voltage is higher than the low voltage.

Description

technical field [0001] The present disclosure relates to an interface to a memory circuit; in particular, an interface to a memory circuit capable of operating with low voltage swing signals. Background technique [0002] A single-chip system (system on chip; SoC) can integrate most or all of a computer's components on a single chip, thus providing an efficient solution in a smaller size. Due to the above advantages, SoCs have been used in various applications such as Display Driver Integrated Circuit (DDIC), Microcontroller Unit (MCU), Bluetooth True Wireless, and Edge-AI . [0003] In order to improve computational efficiency, a static random access memory (Static Random Access Memory, SRAM) circuit is often embedded in an SoC. However, integrating the SRAM into the same die as the SoC not only increases the cost and complexity of the SoC, but also reduces the die yield. While external Dynamic Random Access Memory (DRAM) or Pseudo SRAM (PSRAM) can provide a more cost-ef...

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Problems solved by technology

However, integrating SRAM into the same die as the SoC will not only increase the cost and complexity of the SoC, but also reduce the yield of the die

Although external DRAM (Dynamic Random Access Memory, DRAM) or virtual SRAM (Pseudo SRAM, PSRAM) can provide a more cost-effective solution, the high-speed, high-swing signals used to control external DRAM or PSRAM will Lead to increased power consumption and high electromagnetic interference (Electromagnetic Interference, EMI) problems

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