A
memory module configuration has been developed, which employs multi-level sensing, low-
voltage-swing differential
signal paths, and array
layout techniques to better optimize area / speed / power tradeoffs. In some configurations two-level sensing is employed with secondary sense amplifiers positioned toward a middle of the
memory module with memory banks or submodules positioned therearound. Primary sense-amplifiers in the submodules or banks sense differential signals on local bit-lines spanning the corresponding submodule or
bank and drive a low-
voltage-swing differential
signal onto global bit-lines that span a subset of the submodules or banks. The global bit-lines are sensed by secondary sense amplifiers that drive data outputs across a subset of the submodules or banks toward output circuits. In some configurations the
memory module is divided into upper and lower portions with upper global bit-lines spanning the upper portion and lower global bit-lines spanning the lower portion. Corresponding upper and lower global bit-lines are disjoint and are sensed by corresponding upper and lower secondary sense amplifiers. By this arrangement, the minimum to maximum variation in
access time between the different rows of the memory module is reduced. Moreover, smaller drivers and lower power is achieved by use of such a two-level arrangement. In particular, area reductions and power reductions are achieved for submodule- or
bank-resident primary sense amplifiers.