Shifter register for low power consumption application

Abstract

A high voltage shift register stage which directly accepts low voltage clock signal inputs without using clock buffers. In particular, a shift register stage circuit is adapted to operate with a low voltage swing clock signal, with the stage circuit having a single state node, a, driven directly. This arrangement allows for reduced power consumption and higher operating speeds.

Description

[0001] related application [0002] This application claims the benefit of US Provisional Patent Application No. 60 / 860,059, filed November 20, 2006. This document is incorporated by reference in its entirety for its teachings. technical field [0003] The present invention relates to shift register circuits, and in particular it is suitable for shift register designs that provide the lowest possible power consumption. Background technique [0004] figure 1 A prior design for a single-stage static shift register is illustrated. As with any shift register, the circuit 10 has a signal input in, a clock input ck, and in this architecture complementary outputs out and out * . The circuit is powered by a supply voltage provided by two rail voltages VDD and VSS. [0005] This particular circuit uses an input signal buffer transistor MP1 that feeds a pair of cross-coupled transistors MP2 and MP3 to store the input signal state. Inverters INV1 and INV2 connected to the output ...

AI Technical Summary

Problems solved by technology

However, the voltage swing from the clock input ck may be much smaller (on the order of 3 volts) to reduce power consumption

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