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Memory device for detecting defects by measuring line resistance of word line

A memory and line resistance technology, applied in the direction of measuring devices, digital memory information, measuring electricity, etc., can solve problems such as increased resistance defects, increased resistance distribution, and difficulty in performing contact processes

Pending Publication Date: 2022-06-17
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, it may be difficult to perform a contact process associated with connecting wires, and resistance distribution may increase
Therefore, resistance defects in vertically stacked nonvolatile memory devices may increase

Method used

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  • Memory device for detecting defects by measuring line resistance of word line
  • Memory device for detecting defects by measuring line resistance of word line
  • Memory device for detecting defects by measuring line resistance of word line

Examples

Experimental program
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Embodiment Construction

[0017] Hereinafter, certain embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0018] figure 1 is a block diagram illustrating the memory device 10 according to an embodiment of the inventive concept.

[0019] refer to figure 1 , the memory device 10 may generally include a cell area 20 and a peripheral circuit area 30 . Here, the peripheral circuit area 30 may include a row decoder 31 , a voltage generator 32 , a page buffer 33 , an input / output (I / O) circuit 34 and a control logic 35 .

[0020] The cell area 20 includes memory cells that can be divided into memory blocks (hereinafter, "blocks") BLK1 to BLKn. The blocks BLK1 to BLKn may be connected to the row decoder 31 through a common source line CSL, a string selection line SSL, a word line WL, and a ground selection line GSL, and may also be connected to the page buffer 33 through a bit line BL. For example, in each of blocks BLK1 to BLKn, memory cells arranged at th...

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PUM

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Abstract

A memory device includes; comprising memory cells, a row decoder selecting a word line in response to a received address, and a control logic comprising a sense capacitor having a size proportional to a size of a word line capacitor associated with the selected word line. The control logic measures a line resistance of the selected word line by pre-charging the selected word line, performing a charge sharing operation between the selected word line and the sensing capacitor after pre-charging the selected word line, and measuring a voltage of the sensing capacitor after performing the charge sharing operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS [0002] This application claims priority to Korean Patent Application No. 10-2020-0175296 filed with the Korean Intellectual Property Office on December 15, 2020, the subject matter of which is incorporated herein by reference. technical field [0003] The inventive concepts generally relate to memory devices. Background technique [0004] Non-volatile memory devices in which memory cells are stacked vertically to improve integration have been actively researched. Specifically, as the number of stacked stages increases, so does the height of the metal contact(s) connected to the word line plate. As a result, it may be difficult to perform a contact process associated with connecting wires, and resistance distribution may increase. Therefore, resistance defects in vertically stacked nonvolatile memory devices may increase. SUMMARY OF THE INVENTION [0005] Embodiments of the inventive concept provide memory devices capable ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/04G11C29/50
CPCG11C29/04G11C29/50G11C2029/5004G11C2029/5006G11C16/08H01L2224/08145G11C29/025G11C2029/1202G11C29/12005H01L25/0657H01L25/18H01L2225/06541H01L2225/06562H01L2225/06568G11C8/08G11C8/10G11C16/0483G01R31/31724H01L2924/14511H01L24/08G01R31/31703H01L2924/1431
Inventor 宋皇柱尹才垠李智锡黄相元
Owner SAMSUNG ELECTRONICS CO LTD