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Contact structure in semiconductor device

A semiconductor and contact technology, applied in the field of contact structure, can solve problems such as increasing the complexity of the semiconductor manufacturing process

Pending Publication Date: 2022-06-21
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This scaling down increases the complexity of the semiconductor manufacturing process

Method used

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  • Contact structure in semiconductor device
  • Contact structure in semiconductor device
  • Contact structure in semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0064] Example 1. A method for forming a semiconductor device, comprising: forming a first source / drain (S / D) region and a second S / D region on a first fin structure and a second fin structure, respectively; A first dielectric layer is formed between the first S / D region and the second S / D region; a first gate full surround (GAA) is formed on the first fin structure and the second fin structure, respectively ) structure and a second GAA structure, wherein the first GAA structure and the second GAA structure are electrically isolated by the first dielectric layer; in the first GAA structure and the second GAA structure and the forming a second dielectric layer on the first dielectric layer; forming a tapered trench opening in the second dielectric layer and on the first and second GAA structures and the first dielectric layer; selectively forming a seed layer on the first GAA structure and the second GAA structure and the top surface of the first dielectric layer exposed in the...

example 2

[0065] Example 2. The method of Example 1, wherein forming the tapered trench opening comprises forming a trench opening including a top portion and a bottom portion having substantially vertical sidewalls and a transition portion having sloped sidewalls, wherein the top portion is wider than the bottom portion.

example 3

[0066] Example 3. The method of Example 1, wherein forming the tapered trench openings comprises: forming trench openings having a first width in the second dielectric layer; depositing a masking layer on bottom portions of the trench openings to partially fill the trench openings; and performing on portions of the second dielectric layer exposed in the top portions of the trench openings above the masking layer Etching laterally to form a second width of the top portion that is greater than the first width of the bottom portion.

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Abstract

The invention discloses a contact structure in a semiconductor device. The invention discloses a semiconductor device with an unlined contact structure and a method of manufacturing the same. The method includes forming a first dielectric layer between a first source / drain (S / D) region and a second S / D region formed on the first fin structure and the second fin structure; forming a first gate all-around (GAA) structure and a second GAA structure on the first fin structure and the second fin structure, and forming a second dielectric layer on the first dielectric layer; forming a tapered trench opening in the second dielectric layer and on the first and second GAA structures and the first dielectric layer; selectively forming a seed layer on the exposed first and second GAA structures and a top surface of the first dielectric layer; and selectively depositing a conductive layer on the seed layer.

Description

technical field [0001] The present disclosure relates to contact structures in semiconductor devices. Background technique [0002] As semiconductor technology advances, the need for higher storage capacity, faster processing systems, higher performance, and lower cost continues to increase. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs, fin field-effect transistors (finFETs), and gate-all-around FETs (GAA FETs) . This scaling down increases the complexity of the semiconductor fabrication process. SUMMARY OF THE INVENTION [0003] According to a first aspect of the present disclosure, there is provided a method for forming a semiconductor device comprising: forming a first source / drain (S / D) region and a first source / drain (S / D) region on a first fin structure and a second fin structure, respectively Two S / D regions; a ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8234
CPCH01L21/823475H01L21/823431H01L21/823412H01L29/775H01L27/088H01L21/76804H01L21/76879H01L21/76876H01L21/76865H01L21/76895H01L23/485B82Y10/00H01L29/42392H01L29/66439H01L29/0673H01L29/78696H01L21/76871H01L21/823456H01L23/5226H01L21/76843
Inventor 林秉顺程仲良赵皇麟
Owner TAIWAN SEMICON MFG CO LTD
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