Signal sampling circuit and semiconductor memory

Abstract

The embodiment of the invention provides a signal sampling circuit and a semiconductor memory, and the signal sampling circuit comprises an input sampling circuit which is used for carrying out the sampling processing of a first chip selection signal and a first command address signal according to a first clock signal, and obtaining a second chip selection signal and a second command address signal, the second command address signal comprises an initial command signal; the logical operation circuit is used for performing logical operation on the first clock signal and the second chip selection signal to obtain a chip selection clock signal; the instruction decoding circuit is used for decoding and sampling the initial instruction signal according to the chip selection clock signal and the second chip selection signal to obtain a target instruction signal; and the merging output circuit is used for carrying out sampling and output merging processing on the second command address signal according to the chip selection clock signal to obtain a target address signal. Therefore, time sequence alignment between the target address signal and the target instruction signal can be realized.

Description

technical field [0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a signal sampling circuit and a semiconductor memory. Background technique [0002] With the continuous development of semiconductor technology, people have put forward higher and higher requirements for the transmission speed of data when manufacturing and using equipment such as computers. In order to obtain a faster data transmission speed, a series of devices such as memories that can transmit data at a double rate (Double Data Rate, DDR) have emerged. [0003] In a dynamic random access memory (Dynamic Random Access Memory, DRAM), a command address (Command / Address, CMD / ADD or CA for short) signal can be sampled as an address and can be sampled and decoded as an instruction. In this way, after the CA signal is sampled, since the instruction still needs to be decoded, the instruction path has more logic circuits for decoding than the address path, c...

AI Technical Summary

Problems solved by technology

In this way, after the CA signal is sampled, because the instruction still needs to be decoded, the instruction path has more logic circuits for decoding than the address path, causing the instruction signal and address signal to have a relatively large gap when they reach the next-level functional module. Large timing deviation, which in turn leads to problems with the next-level functional modules due to timing deviation

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