LDO circuit with high power supply rejection
A high power supply suppression and circuit technology, applied in the direction of adjusting electrical variables, control/regulation systems, instruments, etc., can solve the problems of difficult compensation of stability, poor PSR, low loop gain, etc., to reduce output stray, power supply The effect of suppressing high and reducing phase noise
Pending Publication Date: 2022-07-05
GUANGZHOU RUNXIN INFORMATION TECH
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Problems solved by technology
Traditional single-stage LDO has low loop gain and poor PSR
However, due to the need to meet the large-scale changes of the load current, the stability of the multi-level LDO is difficult to compensate.
Method used
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[0029] Hereinafter, the present invention will be further described with reference to the accompanying drawings and specific embodiments. It should be noted that, on the premise of no conflict, the embodiments or technical features described below can be arbitrarily combined to form new embodiments. .
[0030] A high power supply rejection LDO circuit such as figure 1 As shown, including error amplifier EA, secondary amplifier SA, voltage subtractor, buffer Buffer, power tube M P , feedback circuit, load circuit, first compensation circuit, second compensation circuit, the working voltage inside the device and the power supply pin of the error amplifier, the voltage pin of the secondary amplifier, the voltage subtractor, the buffer, the source of the power tube connection, the first reference voltage is connected to the inverting input terminal of the error amplifier, the non-inverting input terminal of the error amplifier is connected to the feedback circuit, the output term...
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The invention provides a high power supply rejection LDO circuit. The high power supply rejection LDO circuit comprises an error amplifier, a secondary amplifier, a voltage subtractor, a buffer, a power tube, a feedback circuit, a load circuit, a first compensation circuit and a second compensation circuit. According to the invention, the error amplifier of the folded cascode architecture is adopted, so that the problem that the flicker noise performance and the phase margin of the LDO of the architecture are mutually restricted is solved, and the phase noise of the phase-locked loop can be reduced; zero-pole distribution of the system is reasonably distributed, and a Miller compensation capacitor is added, so that the system is stable in a range from full load to no load; through the gains of the secondary amplifier, the voltage subtractor and the buffer circuit, the PSR of the low-frequency band in the LDO is improved by 30 dB with low power consumption cost, and the output stray of a radio frequency chip can be reduced.
Description
technical field [0001] The invention relates to the technical field of integrated circuits, and in particular, to a high power supply suppression LDO circuit. Background technique [0002] In RF chips, circuits such as RF front-end and phase-locked loop are very sensitive to noise. To reduce the crosstalk of digital circuits or DCDC ripples to these sensitive circuits through power supply, low dropout regulators (LDOs) with high power supply rejection (PSR) are usually required. ). Traditional single-stage LDOs have low loop gain and poor PSR. However, the stability of multi-level LDO is difficult to compensate due to the need to meet a wide range of load current changes. Therefore, there is an urgent need for a low dropout regulator (LDO) with high power supply rejection (PSR), which can provide a stable power supply to the noise-sensitive circuits of the chip. SUMMARY OF THE INVENTION [0003] In order to overcome the deficiencies of the prior art, the purpose of the ...
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IPC IPC(8): G05F3/26
CPCG05F3/26
Inventor 郝强宇王日炎周伶俐贺黉胤
Owner GUANGZHOU RUNXIN INFORMATION TECH