Memory bit error rate test system and test method thereof

Abstract

The embodiment of the invention relates to the field of semiconductor testing, and provides a memory bit error rate testing system and a testing method thereof, a memory comprises a memory unit, and the testing system comprises a control unit configured to send a control command to the memory unit; the test unit is configured to control the control unit to send a control command to the storage unit, the test unit sends multi-bit data to the storage unit, the storage unit stores the multi-bit data according to a preset sequence based on the control command, and the test unit reads the multi-bit data from the storage unit according to the preset sequence; and the test unit is also used for taking the data, at the same position in the preset sequence, of the multi-bit data as target data, judging whether the target data stored in the storage unit is the same as the target data read from the storage unit or not, and obtaining the bit error rate of the memory in combination with the total bit number of the multi-bit data. The embodiment of the invention is at least beneficial to reducing the test cost of the bit error rate of the memory and improving the test accuracy of the bit error rate.

Description

technical field [0001] The embodiments of the present disclosure relate to the field of semiconductor testing, and in particular, to a memory bit error rate testing system and a testing method thereof. Background technique [0002] As the transmission rate of the signal becomes higher and higher, the function of the chip becomes more and more powerful, with more pins and higher distribution density. Chip and board-level testing, debugging, and testing are becoming more and more important, and signal testing has become a difficult point. Currently, in order to perform a bit error rate test of a dynamic random access memory (DRAM, Dynamic Random Access Memory), a third-party bit error meter needs to be used to generate specific code patterns and detect bit errors to calculate the bit error rate. [0003] However, the cost of the bit error tester is very high. In addition, when using the bit error tester to test the bit error rate of DRAM, an additional test board needs to be ...

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Problems solved by technology

[0003] However, the cost of the BER tester is very high. In addition, when using the BER tester to test the bit error rate of the DRAM, it is necessary to add an additional test board to establish the sending path and the return path between the BER tester and the port of the DRAM. Increase the cost of using a bit error tester to test the bit error rate of DRAM, and have higher requirements for both the bit error tester and DRAM

Moreover, when using the bit error tester to test the DRAM port, only the DRAM port is involved, not the storage unit in the DRAM, that is, the bit error rate of the tested DRAM port is not affected by the storage unit, resulting in the use of the bit error tester The comprehensiveness of testing the bit error rate of DRAM is low

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