Abnormity test method and system based on virtual instruction set platform, and storage medium

Abstract

The invention discloses an exception test method and system based on a virtual instruction set platform and a storage medium, and the method comprises the steps: S1, building a virtual target system on the virtual instruction set platform according to to-be-tested hardware information; s2, selecting an abnormal test component from an abnormal test component library according to the selected VCPU and the test plan, and generating a dynamic link library file according to the selected abnormal test component; s3, loading a bin file of the control software on the virtual target system, starting the virtual target system to enter a normal operation mode, and confirming that each monitoring variable accords with an expected value; and S4, the engine simulation model upper computer dynamically triggers the abnormal test component through the dynamic link library file, executes an automatic test, and stores an output result of the component. According to the exception testing method, the virtual target system is set up on the virtual instruction set platform for testing, the method is not limited by hardware resources, testing is convenient, and meanwhile testing errors caused by testing environment influences are avoided.

Description

technical field [0001] The invention belongs to the software testing technology in the key safety field, and particularly relates to an abnormal testing method, system and storage medium based on a virtual instruction set platform. Background technique [0002] FADEC control software is an important technology in safety-critical fields. When an exception occurs in the control software, the CPU chip must be able to respond in time and execute exception handling to prevent code from running away or executing wrong instructions. Therefore, exception testing is a must to control software testing. The traditional test method is based on the hardware controller to print the test results through the instrument and the serial port. This method is limited by the serial port protocol and cannot accurately display the register and memory changes. Analysis of the abnormal state of the CPU greatly reduces the reliability and accuracy; in addition, the hardware test needs to cooperate wi...

AI Technical Summary

Problems solved by technology

The traditional test method is based on the hardware controller through instrumentation and serial port printing test results. This method is limited by the serial port protocol and cannot accurately display the register and memory changes. It can only display part of the variable test results, which is difficult to capture from a micro perspective and Analyzing the abnormal state of the CPU greatly reduces the reliability and accuracy; in addition, the hardware test needs to cooperate with the controller, test bench, and adaptation box, etc., and it is not easy to coordinate in a unified manner. The test methods are different, and the reset programming process needs to be repeated, which is inefficient and error-prone

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