Method for improving readability of register model modeling code and storage medium

Abstract

The invention discloses a method for improving the readability of modeling codes of a register model and a storage medium, and the method for improving the readability of the modeling codes of the register model comprises the following steps: creating a UVM register model, deriving a field base class of the UVM register model, and generating subclasses; a series interface method is expanded or newly added in the subclass and used for supporting method calling of enumeration type values; creating an enumeration type variable corresponding to a register field of the preset UVM register model; replacing a field base class with the subclass to reconstruct an example register; and performing read-write access on the register field by using a subclass interface method. According to the method, the readable coding mode of the register field can be improved, repeated browsing of the design document is avoided, the time of design and verification developers is saved, and the working efficiency of the developers is improved.

Description

technical field [0001] The invention relates to the technical field of chip verification, in particular to a method and a storage medium for improving the readability of a code for modeling a register model. Background technique [0002] Usually we will model the registers of the DUT based on the UVM verification method. UVM provides the following register model classes for verification developers to use, including: [0003] Register field: Register field. The function of each bit (field) in the register has a corresponding width (width) and offset (offset), as well as read / write (read / write), read-only (read only), and write-only (writeonly) attributes . [0004] Register: Register. Contains one or more register fields. [0005] Register block: Register block. Corresponding to a specific hardware, it can be understood as a container, which contains one or more registers and one or more register maps. The register model we are talking about actually refers to an instan...

AI Technical Summary

Problems solved by technology

[0012] The above scheme is based on the UVM verification methodology, and it is also the scheme that is usually adopted, but there is a defect that we do not know the meaning of the field value in the register, it is just a series of 0 or 1 signals, and unintuitive and thus difficult to understand

This leads to design and verification developers having to read the design documents back and forth many times to see what the value of the corresponding field represents, and often forget, which greatly reduces the work efficiency of the chip design and verification process

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