Phase-locked loop circuit capable of reducing phase deviation and not increasing operating voltage

A phase-locked loop and circuit technology, applied in the direction of electrical components, automatic power control, etc., can solve problems such as insufficient, achieve the effect of reducing phase offset and avoiding phase offset

Inactive Publication Date: 2004-12-08
NEC ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the structure implements specific measures of the solution, and it is not enough

Method used

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  • Phase-locked loop circuit capable of reducing phase deviation and not increasing operating voltage
  • Phase-locked loop circuit capable of reducing phase deviation and not increasing operating voltage
  • Phase-locked loop circuit capable of reducing phase deviation and not increasing operating voltage

Examples

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Embodiment Construction

[0066] Embodiments of the present invention will be specifically described below with reference to the accompanying drawings.

[0067] Figure 5 It is a block diagram showing the structure of a phase-locked loop circuit according to an embodiment of the present invention. This phase locked loop circuit has a phase frequency comparator 10 , an integrator 20 , a phase controller 21 , a current controlled oscillator 14 , a CTS buffer 15 and a feedback frequency divider 16 .

[0068] The phase-frequency comparator 10 takes the input signal f REF The phase and frequency are respectively related to the feedback signal F from the feedback frequency divider 16 FB The phase and frequency of the signal are compared to generate an increase signal UP and a decrease signal DOWN, both of which indicate the error of the signal. For example, a clock signal from an oscillator (not shown) is used as the input signal f REF . The increase signal UP generated by the phase-frequency comparator...

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Abstract

A PLL circuit includes a comparator (10), an integrator (20), a phase controller (21), a current control oscillator (14) and a feedback frequency divider (16). The comparator (10) compares a phase of an input signal (fREF) with a phase of a feedback signal (fFB) to generate a comparison result. The integrator (20) generates a first current to control an oscillation frequency of an output signal (fOUT) based on the comparison result. The phase controller (21) controls a phase of the output signal (fOUT) based on the comparison result such that a phase difference between the phase of the input signal (fREF) and the phase of the output signal (fOUT) at a lock state is reduced to generate a second current. The current control oscillator (14) generates the output signal (fOUT). The feedback frequency divider (16) performs a frequency division on the output signal (fOUT) to generate the feedback signal (fFB).

Description

technical field [0001] The present invention relates to a PLL (Phase Locked Loop) circuit. More specifically, the present invention relates to a phase locked loop circuit for reducing phase shift without increasing operating voltage. Background technique [0002] In general, a PLL circuit is known as a basic technology used in various fields such as information processing, communication, and the like. Such as figure 1 The conventional PLL circuit shown in FIG. [0003] The phase-frequency comparator 50 takes the input signal f REF The phase and frequency of are respectively related to the feedback signal f output from the feedback frequency divider 55 FB The phase and frequency of are compared to generate one of an increase signal UP and a decrease signal DOWN, which indicates the error between these two signals. For example, a clock signal from an oscillator (not shown) is used as the input signal f REF . The increase signal UP generated by the phase-frequency compar...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/093H03L7/08H03L7/085H03L7/089H03L7/18
CPCH03L7/0896H03L7/0893H03L7/18H03L7/085
Inventor 谷本晋
Owner NEC ELECTRONICS CORP
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