Signal test method for integrated circuit chips

Abstract

A signal detection method suitable for integrated circuit chips, wherein the first integrated circuit chip is responsible for sending a plurality of test samples to detect the second integrated circuit chip. According to the present invention, the first integrated circuit chip outputs a different test sample at a time, and the second integrated circuit chip sequentially receives and latches the output test samples to obtain received data, and then according to the received data and output test samples, the second integrated circuit chip The circuit chip can determine whether the received data is correct; if the received data is incorrect and there is at least one error bit, the second integrated circuit chip will refer to the test type of the test sample and indicate that the signal line corresponding to the error bit has ground bounce noise or Interference problem with power supply bouncing noise.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a method for automatically detecting and fine-tuning the signal quality of an integrated circuit. Background technique [0002] With the advancement of the semiconductor manufacturing process, the operating frequency of the current integrated circuit (IC) chip has been greatly increased compared with the past. Not only that, but the data width it handles has also grown from multiples of 8 bits in the early days to 64, Even 128 bits, although the overall performance of the system can be improved, IC designers, circuit system engineers, circuit layout personnel and printed circuit board (Printed CjrcuitBoard, PCB) manufacturers are also facing more severe challenges. As the speed and density of IC chips become faster and higher, the prevention and control of Electromagnetic Interference (EMI) in the overall circuit system becomes increasingly important. [0003] In high-sp...

AI Technical Summary

Problems solved by technology

Taking an 8-bit signal as an example, if the least significant bit (LSB) is logic "0", when the other signals switch from logic "1" to logic "0" at the same time, that is, the signal changes from "11111110" to "00000000" In an instant, the potential of the ground pin of the IC chip changes due to parasitic inductance, causing the ground potential of the IC chip to generate bouncing noise, such as figure 1 As shown, if the rebound voltage is too large, it is likely that the receiving end will misjudge the least significant bit as a logic "1"; When it reaches logic "1", that is, the moment the signal changes from "10000000" to "11111111", the power supply pin of the IC chip causes a potential change due to parasitic inductance, which causes the power supply potential of the IC chip to generate bouncing noise, such as figure 2 As shown, if the sinking voltage is too large, it is likely that the receiving end will misjudge the most significant bit as a logic "0"

If such an error occurs, the slightest case will only reduce the overall performance of the system, but this will make the system unstable and cause crashes

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