Method and apparatus for multistandard video data acquisition

A video data, multi-standard technology, applied in the direction of digital non-picture data transmission, TV, TV system scanning details, etc.

Inactive Publication Date: 2005-06-08
DEUTSCHE THOMSON-BRANDT GMBH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] Conventional video data acquisition circuits can only generate qu

Method used

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  • Method and apparatus for multistandard video data acquisition
  • Method and apparatus for multistandard video data acquisition
  • Method and apparatus for multistandard video data acquisition

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Embodiment Construction

[0029] Figure 1 shows a block diagram of a digital acquisition integrated circuit. An integrated circuit includes a sequential circuit. Vertical and horizontal sync pulses VSYNC and HSYNC are fed into this timing circuit, and at the same time, the timing circuit generates signals CLAMP and LINE_NO. This integrated circuit also includes I 2 C bus interface 101, memory interface 102, VBI address generator VBI_AG, slicer, decoder and VBI buffer.

[0030] Digital acquisition provides the data passed on the VBI of the video signal to the microprocessor. If an internal digital slicer is used, the slicer will scan the incoming CVBS or Y signal as data for the multiplexed incoming video stream. This internal slicer transmits recorded data in a format similar to when it is used as an external teletext slicer. Thus the microprocessor can easily select from which data source the data is retrieved. But data already in digitized format is also included in clipped video data. So the d...

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Abstract

For multi-standard video data acquisition, a decoder with a register 201 of 24 cells to store 3x8 bits of data is employed. The first byte of the 3 bytes is also connected to the logic device in order to compare the contents of the cell with a given start code. The beginning of the register is byte 3, followed by byte 2 and byte 1. Additionally, a second 8-bit register 202 is connected to register 201 in parallel. The content of byte 3 is also fed to weighted average (8/4) decoder 234 and byte 2 to weighted average (8/4) decoder 204 . The 4-bit output of each decoder is fed to the 4 bits specified by register 202, respectively.

Description

technical field [0001] The invention relates to a method and an instrument for collecting multi-standard video data. Background technique [0002] Existing video data slicers have the capability to digitize received signals from different video systems and data services. They provide serial digitized data and clock signals for synchronous data transmission. These data must be queried for valid start codes for a given service or several services in parallel. [0003] Conventional video data acquisition circuits can only generate query serial data streams for a single service-specified start code. For more than one service the "Integrated Video Input Processor" (SAA5281 manufactured by Philips) is limited to a given video system (625 lines) and uses different single standard capture circuits in parallel. Contents of the invention [0004] The purpose of the invention is to disclose a method for collecting multi-channel standard video data. [0005] A further object of th...

Claims

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Application Information

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IPC IPC(8): H04N7/035H04N7/025H04N5/46H04N7/00H04N7/03H04N7/088
CPCH04N7/007H04N7/035H04N7/0885H04N7/0887H04N21/434
Inventor 马克西米利安·埃贝尔林纪南
Owner DEUTSCHE THOMSON-BRANDT GMBH
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