Memory assembly and its making method
A memory and device technology, applied in the fields of semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., which can solve the problems of limited number of semiconductor chips and difficulty in designing memory components with high-speed interfaces.
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Embodiment 1
[0049] 1 shows the structure of a memory module according to Embodiment 1 of the present invention, wherein FIG. 1A is a plan view, FIG. 1B is a side view, and FIG. 1C is a sectional view along the A-A section of FIG. 1A; figure 2 It is an enlarged partial cross-sectional view, showing part B in the cross-sectional view of Fig. 1C on an enlarged scale; Fig. 3 is a circuit block diagram of the memory assembly shown in Fig. 1; Figure 4 is a perspective view showing the structural appearance of a wafer handling package (protruding terminal semiconductor device) mounted on the memory component shown in FIG. 1; FIG. A lead terminal semiconductor device has a surface mount type semiconductor device with lead terminals) and a structure of a wafer handling package, wherein FIG. 5A is a plan view of an SMD, and FIG. 5B is a plan view of a wafer handling package; Image 6 is a process flow showing the manufacturing steps of a wafer handling package mounted on the memory module shown in...
Embodiment 2
[0206] Figure 19 The plan view shows the structure of a memory module according to Embodiment 2 of the present invention.
[0207] The memory package 600 of Embodiment 2 includes 72 WPP10 (protruding terminal semiconductor devices), which are DRAMs mounted in a matrix. The connection of input / output signals to WPP10 is realized in such a way that a group (cluster) includes a total of 9 WPP10s, consisting of one ECC and 8 in 2 rows (in Figure 19 In the memory module 600 of the memory module 600, the direction parallel to the short side of the module board 2 is called a row, and the direction at right angles to it is called a column, but it can also be opposite to the above), and the WPP10 of each group is installed as a memory selection device 9 FET (Field Effect Transistor)-bus switches 15 (lead terminal semiconductor devices) to switch each group.
[0208] That is, in the memory module 600, the connection of the input / output signal to 9 WPP10 in two rows is switched in gr...
Embodiment 3
[0214] FIG. 20 shows the structure of a memory module according to Embodiment 3 of the present invention, wherein FIG. 20A is a plan view, and FIG. 20B is a side view, Figure 21 is a block circuit diagram of the memory component shown in Figure 20, Figure 22 is a bottom view showing the structure of a wafer handling package (protruding terminal semiconductor device) mounted on the memory module shown in FIG. 20, Figure 23 is a wiring diagram on one side of the board showing an example of wiring at part C on the module board in the memory module shown in FIG. 20A , Figure 24 , 25 and 26 are wiring diagrams showing a modified example of a bump arrangement on a wafer handling package in a memory module according to Embodiment 3 of the present invention and a modified example of wiring on the board side corresponding thereto, and FIG. 27 is a bump arrangement. block arrangement and wiring diagram, showing the Figure 25 A further modified example of the bump arrangement on th...
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