Preparation method of tunnelling oxidized layer in imbedded type quick flash storage

Abstract

A process for preparing the tunnelling oxidized layer in embedded flash memory includes such steps as washing the silicon chip, using dry etching machine to fluorinate it, conventional washing, washing it in the solution of isopropanol for 1 min, and high-temp oxidizing.

Description

technical field [0001] The invention belongs to the field of semiconductor devices, and relates to a method for preparing a tunnel oxide layer in an embedded flash memory suitable for SOC (System On A Chip) applications. Background technique [0002] With the development of semiconductor integrated circuit technology, the feature size of the device is continuously reduced, and the operating voltage and power consumption of the device are continuously reduced. In the stacked gate flash memory, as the feature size of the device is reduced or a new device structure , the source-drain operating voltage can be effectively reduced, while the gate voltage strongly depends on the capacitive coupling ratio of the control gate and the floating gate, the thickness of the tunnel oxide layer, the barrier height of the tunnel oxide layer, and the stress-induced leakage current (Stress Induced LeakageCurrent, SILC) and abnormal leakage current (Anomalous Leakage Current). In general flash...

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Problems solved by technology

In general flash memory devices, the thickness of the tunneling oxide layer should not be less than 7 nanometers, mainly because the tunneling oxide layer smaller than 7 nanometers will have a large stress-induced leakage current and abnormal leakage current during device reading and writing, thus affecting The reliability of the device, so the thickness of the tunnel oxide layer is limited; and for the use of some methods to improve the capacitive coupling rate between the control gate and the floating mountain, for the process technology of 0.35 microns and below, these complex process technologies are also Therefore, in reducing the gate voltage of flash memory devices suitable for SOC applications, the preparation of tunnel oxide layers with low barrier heights has become a promising approach. Technology

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