Mesolayer window etching process in the identical etching chamber

Abstract

The mesolayer window etching process in the identical etching chamber includes providing one substrate with dielectric layer, forming one pattern mask with opening on the dielectric layer, etching the dielectric layer in the etching chamber with pattern mask as etching mask to form mesolayer window in the dielectric layer; oxygen treating in the identical etching chamber to eliminate partial pattern mask near the mesolayer window while maintaining the contour of the mesolayer window; and etching the dielectric layer in the same etching chamber with the residual pattern mask as etching mask to expand the upper part of the mesolayer window. The mesolayer window etching process in the identical etching chamber has saving time technological period.

Description

technical field [0001] The present invention relates to an etching process for forming vias, and in particular to a method for etching vias in the same etching chamber. Background technique [0002] In the current manufacturing method of multiple interconnects in the semiconductor process, in order to enhance the step coverage (Step Coverage) capability of the conductor layer filled in the via hole, usually by Figure 1A ~ Figure 1C The method shown makes vias. [0003] Figure 1A ~ Figure 1C Shown is a schematic diagram of a conventional manufacturing process of via holes. [0004] Please refer to Figure 1A , depositing a dielectric layer 102 on a substrate 100 . Then, a patterned photoresist layer 104 is formed on the dielectric layer 102 , and an opening 106 is formed in the patterned photoresist layer 104 . [0005] Then, please refer to Figure 1B , in a wet etching (Wet Etching) chamber, using the patterned photoresist layer 104 as an etching mask, the dielectric ...

AI Technical Summary

Problems solved by technology

[0007] However, the above-mentioned known manufacturing method must use more than two etching chambers to complete the via hole because two completely different etching processes are performed.

Therefore, the known technology needs to spend more process time, and also increases the probability of damage to the chip when it is transferred from one etching chamber to another etching chamber

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