Device and method for parallel testing semiconductor device
A semiconductor and device technology, applied in the direction of single semiconductor device testing, semiconductor/solid-state device testing/measurement, measuring devices, etc.
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[0022] see figure 1 , which shows an apparatus capable of parallel testing on a chip including logic and embedded memory. An essential element of the apparatus provides independent timing of the logic and memory test sequences. The independent clocking capability allows loading of logic test patterns and results in independent offloading of the memory test clocking requirements. The timing signal is provided by the external tester 10 to the clock multiplier and control circuit 11 . During the test process 20, the clock multiplier circuit 11 provides test clock signals 12, 13, 14 to provide independent clock signals to the logic part 21 and the BIST on the memory macro part 23 of the chip.
[0023] In an optional scheme, the clock signal from the tester 10 can be applied to the clock generator 25, and this clock generator 25 can directly generate the clock signal 12, 13, 14 or provide the clock multiplier control circuit 11 A signal which in turn generates said clock signals...
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