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Method for producing transistor

A technology of transistors and bodies, applied in the direction of transistors, semiconductor/solid-state device manufacturing, electric solid-state devices, etc.

Inactive Publication Date: 2007-01-10
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Each transistor has multiple layers

Method used

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  • Method for producing transistor
  • Method for producing transistor
  • Method for producing transistor

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Embodiment Construction

[0024] One embodiment of a fabrication process for fabricating a transistor is described below in detail, however fabricating two MOSFET transistors as CMOS transistors is briefly described according to some embodiments. The first active area of ​​the first transistor and the second active area of ​​the second transistor are demarcated by, for example, forming active area isolation in the substrate. The first active region includes a first delimiting layer of material layer coextensive with the first active region. To form the first defining layer of material, for example, a first material layer may be formed before forming the active area isolation, and then the first material layer is divided by the forming process of the active area isolation. The first material layer may be a gate oxide and doped polysilicon layer.

[0025]A masking layer is then formed over the first and second active regions, and selected portions of the masking layer are removed to expose the second ac...

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Abstract

A method is provided for fabricating a first and second MOSFET transistors in different electrically isolated active areas of a semiconductor body, each one of the transistors having a plurality of layers. A first gate oxide layer and a first poly-crystalline silicon layer are deposited over the semiconductor body over the active areas. Said semiconductor body delineate the first and second active areas, thereby forming first delineated gate oxide layer and poly-crystalline silicon layers coextensive with the first active area. Material is deposited in said trenches to form the active area isolations, the active area isolations having a top surface above said semiconductor body. A masking layer is then formed over said first and second active areas and selective portions of it are removed to expose said second active area. A second gate oxide layer and a second poly-crystalline layer are formed, such second layer and second poly-crystalline layer being coextensive with the second active area. A first transistor and a second transistor are formed.

Description

technical field [0001] The present invention relates to methods of manufacturing transistors, namely Complementary Metal Oxide Field Effect Transistors (CMOS FETs). Background technique [0002] The cost and yield of the manufacturing process of semiconductor chips depends on various factors. One factor is the number of masks (mask layers) used during the process. An increase in the number of masks used in a process generally increases the cost of the process. Another factor is the extent to which the process uses self-aligning processing steps or misalignment tolerance structures. A misalignment tolerant structure is a structure that is manufactured with a high degree of misalignment tolerance from previously formed or subsequently formed structures. Clearly, the self-alignment step or misalignment tolerance structure increases the yield of the manufacturing process by reducing the number of unusable chips due to misalignment. Therefore, it is generally preferred to red...

Claims

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Application Information

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IPC IPC(8): H01L21/8238H01L21/336H01L29/78H01L21/762H01L21/8242H01L27/085H01L27/092H01L27/108
CPCH01L21/762H01L21/823878H01L27/085
Inventor R·伦加拉亚J·贝因特纳尔U·格吕宁H·-O·约阿希姆
Owner INFINEON TECH AG
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