Layout of static RAM units and device

Abstract

SRAM cells and devices are provided. The SRAM cells may share connections with neighboring cells, including ground, power supply voltage and / or bit line connections. SRAM cells and devices are also provided that include first and second active regions disposed at a semiconductor substrate. Parallel first and second gate electrodes cross over the first and second active regions. One end of the first active region adjacent to the first gate electrode is electrically connected to the second active region adjacent to the first gate electrode through a first node line parallel to the first gate electrode, and the other end of the first active region adjacent to the second gate electrode is electrically connected to the second active region adjacent to the second gate electrode through a second node line parallel to the second gate electrode. The first node line is electrically connected to the second gate electrode through a first local interconnection crossing over the first node line, and the second node line is electrically connected to the first gate electrode through a second local interconnection crossing over the second node line. Additionally, a word line may be in direct contact with gate electrodes of transfer transistors of the SRAM cells.

Description

technical field [0001] The present invention relates to a semiconductor device, and more particularly, to a complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell. Background technique [0002] Memory devices are widely used in electronic devices to store data. Typically, such memory devices can be divided into at least two categories: dynamic random access memory (DRAM) and static random access memory (SRAM). DRAM generally refreshes the data periodically by rewriting data into the memory to keep the data. In contrast, SRAM generally does not require this refresh. For example, SRAM devices are widely used in cache memory in computers and portable equipment. [0003] Generally, memory cells of an SRAM device can be divided into two categories. One type of memory cell includes a load resistor as a load device of the memory cell. The other type is a CMOS type unit that uses a transistor as the load device of the memory unit. [0004] Memor...

AI Technical Summary

Problems solved by technology

However, traditionally, full CMOS SRAM cells generally occupy a larger area than corresponding load resistor cells or thin film transistor (TFT) cells

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