Configuration memory implementation for lut-based reconfigurable logic architectures

A technology for reconfiguration and memory cells, applied in the field of address decoders, which can solve problems such as affecting the quality of terminal equipment

Inactive Publication Date: 2007-04-18
NXP BV
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  • Abstract
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  • Claims
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Problems solved by technology

Therefore, the implementation of configurable memory in reconfigurable logic

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  • Configuration memory implementation for lut-based reconfigurable logic architectures
  • Configuration memory implementation for lut-based reconfigurable logic architectures
  • Configuration memory implementation for lut-based reconfigurable logic architectures

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[0032] Therefore, first, some currently known related solutions will be described in more detail. Then, embodiments according to the present invention will be described in more detail. The configuration memory architecture and its implementation are largely determined by the programming method chosen for any RL device. In current RL equipment, three basic programming (configuration) methods can be identified. They are:

[0033] 1. Serial configuration

[0034] 2. Parallel configuration

[0035] 3. Serial-parallel configuration.

[0036] Figure 1 schematically shows a reconfigurable device, which is reconfigured in a serial configuration method. According to this method, the programming of the RL device is performed serially. To achieve this, the configuration storage units c of all tiles b of the device a are connected in a single long scan chain. The data bits in such a scan chain are shifted by successive clock pulses. The advantage of this scheme is that only two pins are requi...

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Abstract

A reconfigurable processing unit (1) is described which comprises, data flow controlling elements (10), data manipulating elements (20), a configuration memory unit (30) comprising a plurality of memory cells (31a, ....) for storing settings of the data flow controlling elements (10) and an addres decoder (40) for converting an address into selection signals for the memory cells (31a, ..). The reconfigurable processing unit of the invention is characterized in that the address decoder (40) is shared between the configuration memory unit (30) and a further memory unit (20), or between two configuration memory units (30, 30'). This provides for a reduction in memory area of the reconfigurable processing unit (1).

Description

technical field [0001] The invention relates to a reconfigurable processing unit, comprising a data flow control element, a data manipulation element, a configuration memory unit including a plurality of storage units for storing settings of the data flow control element, and a configuration memory unit for converting addresses into Address decoder for cell select signals. Background technique [0002] Reconfigurable logic devices include data flow control elements, such as multiplexers, demultiplexers, gates, etc., and data manipulation elements, such as logic gates, adders, and look-up tables, or elements that can be so configured . The latter allows implementing different functions, which can be easily redefined by loading them with different configuration content. The reconfigurable logic device further includes a configuration memory unit (configuration memory) for storing settings of data flow control elements, such as multiplexers, demultiplexers, switches, etc. In...

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Application Information

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IPC IPC(8): H03K19/173H03K19/177G06F15/78
CPCG06F15/7867H03K19/1776
Inventor K·赖坦-诺瓦克
Owner NXP BV
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