Low-power bus interface

Abstract

A system is configured to disable the bus interface of target devices during periods of inactivity on a bus. A bus controller processes data and control signals from an initiator to establish an initiator-to-target communications path for data-transfer to or from the initiator. At the same time that the bus controller is processing the data and control signals, an activity detector notes the occurrence of the request from the initiator, and enables the bus interface on each of the targets. When the target signals a completion of the data-transfer operation, the activity detector notes the occurrence of the completion signal from target and disables the target interfaces of each target. To provide a substantial reduction in power consumption, the enabling and disabling of the target interfaces is effected by controlling the propagation of the clock system clock to each target interface. The single activity detector is continually active, to detect each data-transfer initiation as it occurs, and effectively eliminates the need for each of the individual target bus interfaces to perform this continual monitoring function.

Description

technical field [0001] The invention relates to the field of system and circuit design, in particular, relates to a bus interface control structure considering low power consumption. Background technique [0002] For ease of understanding, the invention is presented using the paradigm of an "initiator" of a bus transaction and a "target" communicating with the initiator. Functional components on the bus can be initiators or targets or both. For example, storage components are usually targets only, because storage components generally do not initiate data transfers. In contrast, the CPU in a uniprocessor system is usually the initiator, since it generally determines what communication will take place. However, if the CPU enables interrupts via the bus structure, it is targeted to the originator of the interrupt. Note that with this paradigm, the roles as initiator and target are independent of the intended direction of data transfer (read / write, send / receive). [0003] Tr...

AI Technical Summary

Problems solved by technology

While this power-saving technique can substantially reduce the power used by the bus fabric, it introduces latency every time a bus transfer is initiated while the clock is reset to its original high-speed operation

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