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Semiconductor device and its mfg. method

A semiconductor and device technology, applied in the field of semiconductor devices, can solve problems such as uneven arrangement of false patterns, and achieve the effect of improving yield and reliability

Inactive Publication Date: 2007-05-16
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the false pattern arrangement in the grid table over the entire wafer surface causes the non-uniformity of the false pattern arrangement in the chip area

Method used

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  • Semiconductor device and its mfg. method
  • Semiconductor device and its mfg. method
  • Semiconductor device and its mfg. method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0024] 5 is a plan view showing a pseudo-pattern arrangement in a semiconductor device according to a first embodiment of the present invention; more specifically, a plan view showing a pseudo-pattern arrangement in a semiconductor device using a trench structure to form wiring.

[0025] Referring to FIG. 5, a division line region 2 having a width of 100 [mu]m is provided on the periphery of a chip region 1 formed on a silicon wafer. In the "diagonal forward jump arrangement" of the chip area 1, square dummy patterns 3 each having a side length of 2 µm are arranged.

[0026] More specifically, as shown in FIG. 6 , the dummy patterns 3 are arranged in a grid that can be repeated horizontally and vertically on the entire surface of the chip region 1 . Each grid is composed of 5×5 squares (a total of 25 squares), and each square has a side length of 1.7 μm in the horizontal and vertical directions. In this arrangement, the dummy patterns 3 are not uniformly arranged in the horiz...

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PUM

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Abstract

In the semiconductor device of the present invention, a plurality of dummy patterns are formed in a grid arrangement in the scribe line areas of a wafer, and a plurality of dummy patterns are formed in a diagonally forward skipped arrangement in the chip interior areas of the wafer. Altering the arrangement of dummy patterns in the chip interior areas and scribe line areas in this way enables formation of dummy patterns with greater uniformity in the chip interior areas and enables formation of dummy patterns with greater resistance to loss that occurs when dicing in scribe line areas.

Description

technical field [0001] The present invention relates to a semiconductor device and a method of manufacturing the device; and more particularly to a semiconductor device in which a dummy pattern is formed on a wiring layer and a method of manufacturing the device. Background technique [0002] In a conventional method of manufacturing a semiconductor device with multiple interconnection layers, when a method in which a trench is filled with a metal is used to form a wiring layer, chemical mechanical polishing (CMP) is used to remove impurities other than those already embedded in the trench. unnecessary metal. In this case, the wiring pattern that has been unevenly formed on the wafer will cause variations in the polishing rate. And there should be a measure to limit the film thickness variation of the final formed line. For this purpose, one method traditionally used is to arrange dummy patterns on the formal wiring layer. The pseudo-pattern referred to here refers to a w...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/70H01L23/52H01L21/301H01L21/3205H01L21/321H01L21/44H01L21/768H01L21/78H01L21/82H01L21/822H01L23/48H01L23/544H01L23/58H01L27/04
CPCH01L2924/0002H01L23/585H01L21/78H01L21/7684H01L2924/00
Inventor 松本明井口学深濑匡
Owner RENESAS ELECTRONICS CORP