A method for depositing a metal layer on a semiconductor interconnect structure having a capping layer

Abstract

Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

Description

[0001] related application [0002] This application is related to US Patent Application 10 / 318,605, entitled "A Method for Depositing a Metal Layer on a Semiconductor Interconnect Structure," filed on the same date as this application. technical field [0003] The present invention relates to semiconductor processing, and more particularly to the processing of semiconductor wafers containing advanced interconnect structures using copper metallurgy. Background technique [0004] Advanced interconnect structures using copper metallurgy exhibit many technological advantages related to functional properties. The most important of these advantages are the realization of stable low contact resistance under thermal cycling, and good reliability under electromigration and stress migration. [0005] Electromigration is the movement of ions in a conductor such as copper in response to the passage of electrical current and can eventually lead to open circuit failure of the conductor....

AI Technical Summary

Problems solved by technology

Disadvantageously, all solutions known to the inventors to the electromigration and TDDB problems involve depositing a metal layer or successive metal layers without taking into account the sputtering step between successive metal layer depositions

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