Unlock instant, AI-driven research and patent intelligence for your innovation.

Semiconductor device and method for fabricating the same

A semiconductor and conductive type technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., and can solve the problem of increasing the number of processes

Inactive Publication Date: 2007-08-08
KK TOSHIBA
View PDF9 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0023] As mentioned above, unlike planar power MOSFETs, conventional superjunction power MOSFETs can achieve both low on-resistance and high withstand voltage. However, compared with planar power MOSFETs, there are steps The problem of a substantial increase in the number of

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor device and method for fabricating the same
  • Semiconductor device and method for fabricating the same
  • Semiconductor device and method for fabricating the same

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0062] 1 to 7 are cross-sectional views showing a method of manufacturing a power MOSFET according to a first embodiment of the present invention. Here, a vertical power MOSFET (DTMOS: Deep Trench MOSFET) having a new withstand voltage structure capable of securing a medium-to-high withstand voltage of 200 V or higher will be described.

[0063] First, as shown in Figure 1, as n + type drain layer with high impurity concentration n + Type Si substrate 1, making the impurity concentration low (high resistance) n - Type epitaxial Si layer 2 growth.

[0064] no + The impurity concentration of Si substrate 1 is, for example, 1×10 19 atom / cm 3 As above, the resistivity is, for example, 0.006 Ω·cm or less. no - The thickness of the epitaxial Si layer 2 is, for example, 50 microns.

[0065] Next, as shown in Figure 2A, using photolithography and RIE (reactive ion etching), in n - type epitaxial Si layer 2 is opened up to n + Type Si substrate 1 deep groove 3.

[0066] The ...

no. 2 example

[0110] Fig. 17 is a sectional perspective view showing a power MOSFET according to a second embodiment of the present invention. 1 to 16 are denoted by the same reference numerals, and detailed description thereof will be omitted (the same applies to the third and subsequent embodiments).

[0111] This embodiment differs from the first embodiment in that the pattern (planar pattern) of the npn column structure seen from above is in a so-called offset mesh shape. If such a structure is adopted, the channel density can be increased according to the element size. In addition, the pattern (planar pattern) of the npn column structure seen from above may also be in a so-called mesh shape (in FIG. 17, the upper and lower npn column structures have a shape that does not deviate in the lateral direction).

no. 3 example

[0113] Fig. 18 is a sectional perspective view showing a power MOSFET according to a third embodiment of the present invention.

[0114] The difference between this embodiment and the first embodiment lies in that n-type column layer 5 with high impurity concentration is formed on the surface of n-type column layer 5. + Type diffusion layer 17.

[0115] in no n + In the case of the n-type diffusion layer 17, when a voltage is applied between the source and the drain, the depletion layer spreads on the surface of the n-type column layer 5. Therefore, if charges such as Na ions adhere to the surface of the n-type column layer 5, the depletion is locally hindered, and the electric field is concentrated on the portion where the depletion is hindered, which may cause breakdown.

[0116] Unlike this, as shown in this embodiment, if n-type column layer 5 is formed on the surface + The n-type diffusion layer 17 can prevent the depletion layer from spreading on the surface of the n-...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A semiconductor device includes a first conductivity type semiconductor substrate, a vertical unit cell and a separating member. The unit cell includes a second conductivity type semiconductor layer and two first conductivity type semiconductor layers to interpose the second conductivity type semiconductor layer from both side surfaces. A pn junction boundary between the second and first conductivity type semiconductor layer is substantially vertical to the main surface of the semiconductor substrate. A second conductivity type base layer on an upper surface of the second conductivity type semiconductor layer has an impurity concentration higher than the second conductivity type semiconductor layer. A first conductivity type source diffusion layer is on a surface of the base layer. A gate insulating film is formed on the base layer interposed between the source diffusion layer and the first conductivity type semiconductor layer. A gate electrode is formed on the gate insulating film.

Description

technical field [0001] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an improvement of a semiconductor device including a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a method of manufacturing the same. Background technique [0002] FIG. 21 shows a cross-sectional view of a conventional typical power MOSFET. In the figure, 81 represents as n + type drain layer with high impurity concentration n + type Si substrate, the n + Type Si substrate 81 is formed with n - type epitaxial Si layer 82 . [0003] in the n - On the surface of the p-type epitaxial Si layer 82, a p-type base layer 83 is selectively formed, and then on the surface of the p-type base layer 83, n + type source diffusion layer 84 . [0004] by the n + type source diffusion layer 84 and n - A p-type epitaxial Si layer 82 is sandwiched on a p-type base layer 83 in the middle, and a gate 86 is provided sandwi...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L29/78H01L21/265H01L21/336H01L29/40
CPCH01L29/66712H01L21/26586H01L29/7802H01L29/0653H01L29/0696H01L29/407H01L29/0634H01L29/7811
Inventor 都鹿野健一齐藤芳彦上月繁雄碓氷康典泉泽优河野孝弘
Owner KK TOSHIBA