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Circuit device and method for accelerated ageing in magnetoresistance memory

A circuit device, a technology for accelerated aging, applied in static memory, digital memory information, magnetic field controlled resistors, etc. Effect

Inactive Publication Date: 2002-04-17
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, testing of this aging process is very laborious, because aging has to wait for a long time, which is unacceptable if a period of about 10 years is considered, or repeat visits are required, which can be achieved in up to 10 years. 12 In the case of this time, it means huge time and equipment consumption

Method used

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  • Circuit device and method for accelerated ageing in magnetoresistance memory
  • Circuit device and method for accelerated ageing in magnetoresistance memory

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Embodiment Construction

[0012] The memory cell Z composed of the soft magnetic layer WM, the tunnel barrier layer TB and the hard magnetic layer HM is located at the intersection between the word line WL and the bit line BL. The two sides of the word line WL are connected to the control units 1 and 2. The control unit 1 is composed of driving transistors T1 and T2, and the control unit 2 has driving transistors T3 and T4. The driving transistors T1 and T2 are connected in series between the low level (ground potential) and the high level (power supply potential). This method is also applicable to the driving transistors T3 and T4. The gates of the driving transistors T1 to T4 are controlled by control signals A, B, B and A.

[0013] The driving transistors T1 and T3 are p-channel MOS transistors, and the driving transistors T2 and T4 are n-channel MOS transistors.

[0014] According to the signals A, B and A, B on the gate of the drive transistor, low and / or high levels are applied to the nodes K1 and K2...

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Abstract

A circuit configuration and a method for accelerating aging in an MRAM, in which additional means are provided in order to feed a higher current into a control line of a memory cell which is located nearer the soft-magnetic layer.

Description

Technical field [0001] The present invention relates to a circuit device and method for accelerating aging in MRAM (MRAM = magnetoresistive memory). The MRAM has a memory cell area in which a number of soft magnetic layers are arranged at the intersection of two control lines And the storage unit of the hard magnetic layer, and the control signal can always be fed to the two control lines through the first control unit. Background technique [0002] As we all know, the MRAM cell is composed of a soft magnetic layer, a tunnel barrier layer and a hard magnetic layer. These layers are located between two crossing control lines, that is, a word line and a bit line, and are stacked in the crossing point. In these MRAM cells, writing is performed in the normal operating mode by the superimposed magnetic field generated by the current flowing through the control line. Here, the hard magnetic layer maintains its magnetization direction, while the magnetization direction in the soft magne...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/30G01R31/28G11C11/14G11C11/15G11C29/06G11C29/50H01L43/08H10B20/00
CPCG11C29/50G11C11/16G11C11/15
Inventor H·赫尼施米德
Owner INFINEON TECH AG