Semiconductor storage device

Abstract

To increase utilizable memory capacity by utilizing the conventional dummy array in a semiconductor memory device having open bit line structure for data storage. A bit line folding type sense amplifier circuit 33 is provided at the outer side of an end part memory cell array 20 in which 2Tr1C type cells constituted of a data accumulating capacitor 3, an A port access transistor 4a, and a B port access transistor 4b are constituted in a matrix state, and word lines for selecting a cell are connected to gates of corresponding transistors 4a, 4b. A drain of the A port access transistor 4a is connected to any bit line of a bit line open type sense amplifier circuit 32, and a drain of the B port access transistor 4b is connected to any bit line out of the pair of bit line of the bit line folding type sense amplifier circuit 33.

Description

Technical field [0001] The present invention relates to a semiconductor storage device, in particular to a DRAM (dynamic random access memory). Background technique [0002] A 2-port DRAM cell is disclosed in US Patent No. 5,923,593. According to this patent, a DRAM cell is a 2-transistor·1 capacitor (2Tr1C) type cell composed of two access transistors and one data storage capacitor. If the two ports used to access the data storage capacitor in the DRAM cell are called A port and B port, the above two access transistors are called A port access transistor and B port access transistor, respectively. The A-port access transistor includes a source connected to one electrode of the data storage capacitor, a gate connected to the A-port word line, and a drain connected to the A-port bit line. The B port access transistor includes a source connected to the same electrode of the data storage capacitor, a gate connected to the B port word line, and a drain connected to the B port bit lin...

AI Technical Summary

Problems solved by technology

In this way, the first memory cell array can be accessed through the B port, but the virtual array cannot be accessed

[0005] In the semiconductor memory device of the above-mentioned prior art, the dummy array provides only the reference bit line group with respect to the bit line group of the adjacent memory cell array.

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