Mfg. method of semiconductor device with opening portion

A manufacturing method and semiconductor technology, which can be used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., to solve problems such as metal filling for wiring, disconnection of anti-diffusion films, and reduction in reliability of semiconductor devices.

CN1447414AInactive Publication Date: 2003-10-08SANYO ELECTRIC CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Publication Date
2003-10-08
Estimated Expiration
Not applicable · inactive patent

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Abstract

When an antireflection film is used when forming the two-stage stepped opening on the interlayer insulating film, it is possible to obtain a semiconductor device manufacturing method capable of preventing a decrease in reliability. The manufacturing method of this semiconductor device comprises the steps of forming a first resist pattern on a predetermined region on an antireflective film, using the first resist pattern as a mask to form a first opening in an interlayer insulating film, leaving After removing the first anti-corrosion pattern on the anti-reflection film, in the predetermined area on the anti-reflection film, the process of forming the second anti-corrosion pattern, using the second anti-corrosion pattern as a mask, at least on the top of the first opening, A step of forming a second opening having a larger opening area than the first opening.
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Description

technical field

[0001] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having an opening. Background technique

[0002] In recent years, attempts have been made to simplify the process by using a dual damascene (Dual Damascene) method when forming multilayer wiring of a semiconductor device. This double embedding method is: After forming a via hole and a wiring trench on the interlayer insulating film, by embedding metal in the via hole and wiring trench, simultaneously forming the embedded wiring that becomes the upper wiring layer In this dual damascene method, as a process of forming a via hole and a wiring trench, a plug is obtained to obtain a contact with the underlying wiring layer. After the via hole is formed in the insulating film, the upper portion of the via hole is opened again to form a trench for embedded wiring.

[0003] Usually, the aforementioned v...

Examples

Embodiment Construction

[0032] Next, description will be given based on attached drawings of embodiments of the present invention.

[0033] Implementation form 1

[0034] refer to Figure 1 to Figure 11 , the method of manufacturing the semiconductor device according to the first embodiment will be described. First, if figure 1 As shown, on the surface of the semiconductor substrate 1, MOS transistors and wiring structures connected to the MOS transistors are formed. This MOS transistor includes a pair of source / drain regions 2 formed at a predetermined interval interposed in a channel region, and a gate electrode 4 formed through a gate insulating film 3 on the channel region. In addition, the wiring structure connected to the MOS transistor includes a tungsten plug 6 filled in the via hole 5a formed in the interlayer insulating film 5, and a nitrogen plug formed along the surface of the wiring trench 5b of the interlayer insulating film 5. An anti-diffusion film 7 made of a tantalum oxide (TaN...