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Multi-chip package and producing method thereof

A technology of multi-chip packaging and packaging, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., and can solve problems such as inapplicability to high-speed device products, difficulty in stacking, and increased area of ​​multi-chip packaging

Inactive Publication Date: 2003-11-05
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this regard, if the semiconductor chips 21, 22, 23 are arranged horizontally, there arises a problem that the area of ​​the multi-chip package increases
In addition, if the same type of memory chip is used to increase the storage capacity, there will be a problem that it is difficult to stack due to the same size of the memory chip
[0011] at the same time, figure 1 and figure 2 The multi-chip package shown has the common problem of being unsuitable for high-speed device products because gold wires 16, 26 are used as electrical connection means

Method used

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  • Multi-chip package and producing method thereof
  • Multi-chip package and producing method thereof
  • Multi-chip package and producing method thereof

Examples

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no. 1 example

[0051] A multi-chip package according to a first embodiment of the present invention is shown in image 3 and Figure 17 Perspective and cross-sectional views in . refer to image 3 and Figure 17 , the multi-chip package 100 includes four chips 111, 112a, 112b and 113 (see Figure 11 to Figure 13 ). Three sides of the multi-chip package 100 are surrounded by a circuit substrate 120 , and all semiconductor chips 111 , 112 a , 112 b , and 113 are placed in an inner space 102 of the package defined by an inner surface of the circuit substrate 120 . Each of the semiconductor chips 111 , 112 a , 112 b , and 113 has a plurality of chip bumps 88 formed on its upper surface and physically bonded and electrically connected to the inner surface of the circuit substrate 120 .

[0052] The circuit substrate 120 includes three regions in total. The circuit substrate 120 is folded at the boundaries of these areas; the first area 121 forms an upper surface of the package, the second a...

no. 3 example

[0070] Figure 19 to Figure 22 A multi-chip package 300 and steps of its manufacturing method according to the third embodiment of the present invention are shown, wherein Figure 19 is a plan view of the inner surface of the unit circuit substrate 320, Figure 20 is a plan view of a unit circuit substrate 320 on which semiconductor chips 311, 312a, 312b, and 313 are mounted, Figure 21 is a perspective view of the unit circuit substrate 320 in a folded state, and Figure 22 It is a perspective view showing a state of filling the sealant 340 into the internal space of the package.

[0071] As shown in the figure, different from the previous embodiments, the circuit substrate 320 includes four regions 321 , 322 , 323 and 324 . In particular, the fourth area 324 extends from one side of the third area 323 and is formed in a plug-in socket type. The external connection terminals of the package are a plurality of contact pads 350 formed on one side of the fourth region 324 . ...

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Abstract

The invention discloses a multi-chip packaging body and a manufacturing method thereof. The multi-chip package includes: a circuit substrate including first, second and third regions surrounding three sides of the multi-chip package; and at least two semiconductor chips disposed between inner surfaces of the above-mentioned three regions In a defined interior space of the package, the semiconductor chips are physically bonded to each other and electrically connected to each other. With the multi-chip package, not only the same type of memory chips can be stacked to increase the storage capacity, but also different types of memory chips can be arranged in combination to realize a system package with various functions.

Description

technical field [0001] The present invention relates to a semiconductor package, in particular, to a multi-chip package in which two or more semiconductor chipsets of different sizes and functions are packaged in one package. Background technique [0002] In the semiconductor industry, packaging technology for integrated circuit chips continues to advance. In particular, recent developments in the information and communication industries have led to constant efforts to develop small, lightweight and multifunctional packages. As a result of these efforts, a so-called "multi-chip package" has been proposed. [0003] The multi-chip package increases storage capacity by stacking memory chips of the same size and function, or maximizes product performance and efficiency by combining semiconductor chips of various sizes and functions. For example, two or more DRAMs are stacked to realize a high capacity, and SRAM, flash memory, radio frequency (RF) chips, etc., are simultaneousl...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/12H01L21/50H01L23/02H01L23/48H01L23/492H01L23/538H01L25/00H01L25/065
CPCH01L23/5387H01L25/065H01L25/0657H01L2224/32145H01L2224/4826H01L2225/06517H01L2225/06579H01L2225/06582H01L2924/01078H01L2924/01079H01L2924/14H01L2924/15311H01L24/48H01L2224/32245H01L2224/73215H01L2224/45144H01L2924/00014H01L24/45H01L2924/00H01L2224/45015H01L2924/207H01L23/12
Inventor 崔信
Owner SK HYNIX INC